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2e03285224
Pull ARM updates from Russell King: "This set includes adding support for Neon acceleration of RAID6 XOR code from Ard Biesheuvel, cache flushing and barrier updates from Will Deacon, and a cleanup to the ARM debug code which reduces the amount of code by about 500 lines. A few other cleanups, such as constifying the machine descriptors which already shouldn't be written to, cleaning up the printing of the L2 cache size" * 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (55 commits) ARM: 7826/1: debug: support debug ll on hisilicon soc ARM: 7830/1: delay: don't bother reporting bogomips in /proc/cpuinfo ARM: 7829/1: Add ".text.unlikely" and ".text.hot" to arm unwind tables ARM: 7828/1: ARMv7-M: implement restart routine common to all v7-M machines ARM: 7827/1: highbank: fix debug uart virtual address for LPAE ARM: 7823/1: errata: workaround Cortex-A15 erratum 773022 ARM: 7806/1: allow DEBUG_UNCOMPRESS for Tegra ARM: 7793/1: debug: use generic option for ep93xx PL10x debug port ARM: debug: move SPEAr debug to generic PL01x code ARM: debug: move davinci debug to generic 8250 code ARM: debug: move keystone debug to generic 8250 code ARM: debug: remove DEBUG_ROCKCHIP_UART ARM: debug: provide generic option choices for 8250 and PL01x ports ARM: debug: move PL01X debug include into arch/arm/include/debug/ ARM: debug: provide PL01x debug uart phys/virt address configuration options ARM: debug: add support for word accesses to debug/8250.S ARM: debug: move 8250 debug include into arch/arm/include/debug/ ARM: debug: provide 8250 debug uart phys/virt address configuration options ARM: debug: provide 8250 debug uart register shift configuration option ARM: debug: provide 8250 debug uart flow control configuration option ...
255 lines
6.7 KiB
C
255 lines
6.7 KiB
C
/*
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* linux/arch/arm/kernel/devtree.c
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*
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* Copyright (C) 2009 Canonical Ltd. <jeremy.kerr@canonical.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/export.h>
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#include <linux/errno.h>
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#include <linux/types.h>
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#include <linux/bootmem.h>
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#include <linux/memblock.h>
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#include <linux/of.h>
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#include <linux/of_fdt.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <asm/cputype.h>
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#include <asm/setup.h>
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#include <asm/page.h>
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#include <asm/smp_plat.h>
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#include <asm/mach/arch.h>
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#include <asm/mach-types.h>
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void __init early_init_dt_add_memory_arch(u64 base, u64 size)
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{
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arm_add_memory(base, size);
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}
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void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
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{
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return alloc_bootmem_align(size, align);
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}
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void __init arm_dt_memblock_reserve(void)
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{
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u64 *reserve_map, base, size;
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if (!initial_boot_params)
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return;
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/* Reserve the dtb region */
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memblock_reserve(virt_to_phys(initial_boot_params),
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be32_to_cpu(initial_boot_params->totalsize));
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/*
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* Process the reserve map. This will probably overlap the initrd
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* and dtb locations which are already reserved, but overlaping
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* doesn't hurt anything
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*/
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reserve_map = ((void*)initial_boot_params) +
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be32_to_cpu(initial_boot_params->off_mem_rsvmap);
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while (1) {
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base = be64_to_cpup(reserve_map++);
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size = be64_to_cpup(reserve_map++);
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if (!size)
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break;
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memblock_reserve(base, size);
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}
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}
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/*
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* arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree
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* and builds the cpu logical map array containing MPIDR values related to
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* logical cpus
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*
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* Updates the cpu possible mask with the number of parsed cpu nodes
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*/
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void __init arm_dt_init_cpu_maps(void)
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{
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/*
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* Temp logical map is initialized with UINT_MAX values that are
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* considered invalid logical map entries since the logical map must
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* contain a list of MPIDR[23:0] values where MPIDR[31:24] must
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* read as 0.
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*/
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struct device_node *cpu, *cpus;
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u32 i, j, cpuidx = 1;
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u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
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u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
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bool bootcpu_valid = false;
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cpus = of_find_node_by_path("/cpus");
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if (!cpus)
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return;
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for_each_child_of_node(cpus, cpu) {
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u32 hwid;
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if (of_node_cmp(cpu->type, "cpu"))
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continue;
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pr_debug(" * %s...\n", cpu->full_name);
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/*
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* A device tree containing CPU nodes with missing "reg"
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* properties is considered invalid to build the
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* cpu_logical_map.
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*/
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if (of_property_read_u32(cpu, "reg", &hwid)) {
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pr_debug(" * %s missing reg property\n",
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cpu->full_name);
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return;
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}
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/*
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* 8 MSBs must be set to 0 in the DT since the reg property
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* defines the MPIDR[23:0].
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*/
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if (hwid & ~MPIDR_HWID_BITMASK)
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return;
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/*
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* Duplicate MPIDRs are a recipe for disaster.
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* Scan all initialized entries and check for
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* duplicates. If any is found just bail out.
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* temp values were initialized to UINT_MAX
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* to avoid matching valid MPIDR[23:0] values.
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*/
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for (j = 0; j < cpuidx; j++)
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if (WARN(tmp_map[j] == hwid, "Duplicate /cpu reg "
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"properties in the DT\n"))
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return;
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/*
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* Build a stashed array of MPIDR values. Numbering scheme
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* requires that if detected the boot CPU must be assigned
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* logical id 0. Other CPUs get sequential indexes starting
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* from 1. If a CPU node with a reg property matching the
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* boot CPU MPIDR is detected, this is recorded so that the
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* logical map built from DT is validated and can be used
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* to override the map created in smp_setup_processor_id().
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*/
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if (hwid == mpidr) {
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i = 0;
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bootcpu_valid = true;
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} else {
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i = cpuidx++;
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}
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if (WARN(cpuidx > nr_cpu_ids, "DT /cpu %u nodes greater than "
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"max cores %u, capping them\n",
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cpuidx, nr_cpu_ids)) {
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cpuidx = nr_cpu_ids;
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break;
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}
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tmp_map[i] = hwid;
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}
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if (!bootcpu_valid) {
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pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n");
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return;
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}
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/*
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* Since the boot CPU node contains proper data, and all nodes have
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* a reg property, the DT CPU list can be considered valid and the
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* logical map created in smp_setup_processor_id() can be overridden
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*/
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for (i = 0; i < cpuidx; i++) {
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set_cpu_possible(i, true);
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cpu_logical_map(i) = tmp_map[i];
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pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i));
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}
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}
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bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
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{
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return (phys_id & MPIDR_HWID_BITMASK) == cpu_logical_map(cpu);
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}
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/**
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* setup_machine_fdt - Machine setup when an dtb was passed to the kernel
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* @dt_phys: physical address of dt blob
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*
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* If a dtb was passed to the kernel in r2, then use it to choose the
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* correct machine_desc and to setup the system.
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*/
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const struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys)
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{
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struct boot_param_header *devtree;
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const struct machine_desc *mdesc, *mdesc_best = NULL;
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unsigned int score, mdesc_score = ~1;
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unsigned long dt_root;
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const char *model;
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#ifdef CONFIG_ARCH_MULTIPLATFORM
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DT_MACHINE_START(GENERIC_DT, "Generic DT based system")
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MACHINE_END
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mdesc_best = &__mach_desc_GENERIC_DT;
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#endif
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if (!dt_phys)
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return NULL;
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devtree = phys_to_virt(dt_phys);
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/* check device tree validity */
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if (be32_to_cpu(devtree->magic) != OF_DT_HEADER)
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return NULL;
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/* Search the mdescs for the 'best' compatible value match */
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initial_boot_params = devtree;
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dt_root = of_get_flat_dt_root();
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for_each_machine_desc(mdesc) {
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score = of_flat_dt_match(dt_root, mdesc->dt_compat);
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if (score > 0 && score < mdesc_score) {
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mdesc_best = mdesc;
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mdesc_score = score;
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}
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}
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if (!mdesc_best) {
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const char *prop;
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long size;
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early_print("\nError: unrecognized/unsupported "
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"device tree compatible list:\n[ ");
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prop = of_get_flat_dt_prop(dt_root, "compatible", &size);
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while (size > 0) {
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early_print("'%s' ", prop);
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size -= strlen(prop) + 1;
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prop += strlen(prop) + 1;
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}
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early_print("]\n\n");
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dump_machine_table(); /* does not return */
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}
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model = of_get_flat_dt_prop(dt_root, "model", NULL);
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if (!model)
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model = of_get_flat_dt_prop(dt_root, "compatible", NULL);
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if (!model)
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model = "<unknown>";
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pr_info("Machine: %s, model: %s\n", mdesc_best->name, model);
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/* Retrieve various information from the /chosen node */
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of_scan_flat_dt(early_init_dt_scan_chosen, boot_command_line);
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/* Initialize {size,address}-cells info */
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of_scan_flat_dt(early_init_dt_scan_root, NULL);
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/* Setup memory, calling early_init_dt_add_memory_arch */
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of_scan_flat_dt(early_init_dt_scan_memory, NULL);
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/* Change machine number to match the mdesc we're using */
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__machine_arch_type = mdesc_best->nr;
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return mdesc_best;
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}
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