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d157e9ecec
Patch from Deepak Saxena CLSP7500 map_desc.pfn conversion Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
396 lines
8.1 KiB
C
396 lines
8.1 KiB
C
/*
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* linux/arch/arm/mach-clps7500/core.c
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*
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* Copyright (C) 1998 Russell King
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* Copyright (C) 1999 Nexus Electronics Ltd
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*
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* Extra MM routines for CL7500 architecture
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/serial_8250.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <asm/hardware.h>
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#include <asm/hardware/iomd.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mach-types.h>
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unsigned int vram_size;
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static void cl7500_ack_irq_a(unsigned int irq)
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{
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unsigned int val, mask;
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mask = 1 << irq;
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val = iomd_readb(IOMD_IRQMASKA);
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iomd_writeb(val & ~mask, IOMD_IRQMASKA);
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iomd_writeb(mask, IOMD_IRQCLRA);
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}
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static void cl7500_mask_irq_a(unsigned int irq)
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{
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unsigned int val, mask;
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mask = 1 << irq;
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val = iomd_readb(IOMD_IRQMASKA);
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iomd_writeb(val & ~mask, IOMD_IRQMASKA);
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}
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static void cl7500_unmask_irq_a(unsigned int irq)
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{
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unsigned int val, mask;
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mask = 1 << irq;
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val = iomd_readb(IOMD_IRQMASKA);
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iomd_writeb(val | mask, IOMD_IRQMASKA);
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}
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static struct irqchip clps7500_a_chip = {
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.ack = cl7500_ack_irq_a,
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.mask = cl7500_mask_irq_a,
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.unmask = cl7500_unmask_irq_a,
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};
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static void cl7500_mask_irq_b(unsigned int irq)
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{
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unsigned int val, mask;
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mask = 1 << (irq & 7);
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val = iomd_readb(IOMD_IRQMASKB);
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iomd_writeb(val & ~mask, IOMD_IRQMASKB);
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}
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static void cl7500_unmask_irq_b(unsigned int irq)
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{
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unsigned int val, mask;
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mask = 1 << (irq & 7);
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val = iomd_readb(IOMD_IRQMASKB);
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iomd_writeb(val | mask, IOMD_IRQMASKB);
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}
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static struct irqchip clps7500_b_chip = {
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.ack = cl7500_mask_irq_b,
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.mask = cl7500_mask_irq_b,
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.unmask = cl7500_unmask_irq_b,
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};
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static void cl7500_mask_irq_c(unsigned int irq)
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{
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unsigned int val, mask;
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mask = 1 << (irq & 7);
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val = iomd_readb(IOMD_IRQMASKC);
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iomd_writeb(val & ~mask, IOMD_IRQMASKC);
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}
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static void cl7500_unmask_irq_c(unsigned int irq)
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{
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unsigned int val, mask;
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mask = 1 << (irq & 7);
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val = iomd_readb(IOMD_IRQMASKC);
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iomd_writeb(val | mask, IOMD_IRQMASKC);
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}
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static struct irqchip clps7500_c_chip = {
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.ack = cl7500_mask_irq_c,
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.mask = cl7500_mask_irq_c,
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.unmask = cl7500_unmask_irq_c,
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};
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static void cl7500_mask_irq_d(unsigned int irq)
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{
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unsigned int val, mask;
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mask = 1 << (irq & 7);
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val = iomd_readb(IOMD_IRQMASKD);
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iomd_writeb(val & ~mask, IOMD_IRQMASKD);
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}
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static void cl7500_unmask_irq_d(unsigned int irq)
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{
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unsigned int val, mask;
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mask = 1 << (irq & 7);
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val = iomd_readb(IOMD_IRQMASKD);
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iomd_writeb(val | mask, IOMD_IRQMASKD);
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}
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static struct irqchip clps7500_d_chip = {
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.ack = cl7500_mask_irq_d,
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.mask = cl7500_mask_irq_d,
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.unmask = cl7500_unmask_irq_d,
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};
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static void cl7500_mask_irq_dma(unsigned int irq)
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{
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unsigned int val, mask;
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mask = 1 << (irq & 7);
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val = iomd_readb(IOMD_DMAMASK);
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iomd_writeb(val & ~mask, IOMD_DMAMASK);
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}
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static void cl7500_unmask_irq_dma(unsigned int irq)
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{
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unsigned int val, mask;
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mask = 1 << (irq & 7);
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val = iomd_readb(IOMD_DMAMASK);
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iomd_writeb(val | mask, IOMD_DMAMASK);
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}
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static struct irqchip clps7500_dma_chip = {
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.ack = cl7500_mask_irq_dma,
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.mask = cl7500_mask_irq_dma,
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.unmask = cl7500_unmask_irq_dma,
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};
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static void cl7500_mask_irq_fiq(unsigned int irq)
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{
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unsigned int val, mask;
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mask = 1 << (irq & 7);
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val = iomd_readb(IOMD_FIQMASK);
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iomd_writeb(val & ~mask, IOMD_FIQMASK);
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}
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static void cl7500_unmask_irq_fiq(unsigned int irq)
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{
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unsigned int val, mask;
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mask = 1 << (irq & 7);
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val = iomd_readb(IOMD_FIQMASK);
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iomd_writeb(val | mask, IOMD_FIQMASK);
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}
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static struct irqchip clps7500_fiq_chip = {
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.ack = cl7500_mask_irq_fiq,
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.mask = cl7500_mask_irq_fiq,
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.unmask = cl7500_unmask_irq_fiq,
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};
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static void cl7500_no_action(unsigned int irq)
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{
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}
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static struct irqchip clps7500_no_chip = {
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.ack = cl7500_no_action,
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.mask = cl7500_no_action,
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.unmask = cl7500_no_action,
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};
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static struct irqaction irq_isa = { no_action, 0, CPU_MASK_NONE, "isa", NULL, NULL };
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static void __init clps7500_init_irq(void)
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{
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unsigned int irq, flags;
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iomd_writeb(0, IOMD_IRQMASKA);
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iomd_writeb(0, IOMD_IRQMASKB);
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iomd_writeb(0, IOMD_FIQMASK);
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iomd_writeb(0, IOMD_DMAMASK);
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for (irq = 0; irq < NR_IRQS; irq++) {
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flags = IRQF_VALID;
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if (irq <= 6 || (irq >= 9 && irq <= 15) ||
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(irq >= 48 && irq <= 55))
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flags |= IRQF_PROBE;
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switch (irq) {
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case 0 ... 7:
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set_irq_chip(irq, &clps7500_a_chip);
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set_irq_handler(irq, do_level_IRQ);
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set_irq_flags(irq, flags);
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break;
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case 8 ... 15:
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set_irq_chip(irq, &clps7500_b_chip);
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set_irq_handler(irq, do_level_IRQ);
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set_irq_flags(irq, flags);
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break;
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case 16 ... 22:
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set_irq_chip(irq, &clps7500_dma_chip);
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set_irq_handler(irq, do_level_IRQ);
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set_irq_flags(irq, flags);
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break;
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case 24 ... 31:
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set_irq_chip(irq, &clps7500_c_chip);
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set_irq_handler(irq, do_level_IRQ);
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set_irq_flags(irq, flags);
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break;
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case 40 ... 47:
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set_irq_chip(irq, &clps7500_d_chip);
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set_irq_handler(irq, do_level_IRQ);
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set_irq_flags(irq, flags);
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break;
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case 48 ... 55:
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set_irq_chip(irq, &clps7500_no_chip);
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set_irq_handler(irq, do_level_IRQ);
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set_irq_flags(irq, flags);
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break;
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case 64 ... 72:
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set_irq_chip(irq, &clps7500_fiq_chip);
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set_irq_handler(irq, do_level_IRQ);
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set_irq_flags(irq, flags);
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break;
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}
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}
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setup_irq(IRQ_ISA, &irq_isa);
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}
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static struct map_desc cl7500_io_desc[] __initdata = {
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{ /* IO space */
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.virtual = IO_BASE,
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.pfn = __phys_to_pfn(IO_START),
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.length = IO_SIZE,
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.type = MT_DEVICE
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}, { /* ISA space */
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.virtual = ISA_BASE,
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.pfn = __phys_to_pfn(ISA_START),
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.length = ISA_SIZE,
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.type = MT_DEVICE
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}, { /* Flash */
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.virtual = FLASH_BASE,
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.pfn = __phys_to_pfn(FLASH_START),
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.length = FLASH_SIZE,
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.type = MT_DEVICE
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}, { /* LED */
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.virtual = LED_BASE,
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.pfn = __phys_to_pfn(LED_START),
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.length = LED_SIZE,
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.type = MT_DEVICE
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}
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};
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static void __init clps7500_map_io(void)
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{
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iotable_init(cl7500_io_desc, ARRAY_SIZE(cl7500_io_desc));
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}
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extern void ioctime_init(void);
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extern unsigned long ioc_timer_gettimeoffset(void);
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static irqreturn_t
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clps7500_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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write_seqlock(&xtime_lock);
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timer_tick(regs);
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/* Why not using do_leds interface?? */
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{
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/* Twinkle the lights. */
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static int count, state = 0xff00;
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if (count-- == 0) {
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state ^= 0x100;
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count = 25;
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*((volatile unsigned int *)LED_ADDRESS) = state;
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}
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}
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write_sequnlock(&xtime_lock);
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return IRQ_HANDLED;
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}
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static struct irqaction clps7500_timer_irq = {
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.name = "CLPS7500 Timer Tick",
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.flags = SA_INTERRUPT | SA_TIMER,
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.handler = clps7500_timer_interrupt,
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};
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/*
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* Set up timer interrupt.
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*/
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static void __init clps7500_timer_init(void)
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{
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ioctime_init();
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setup_irq(IRQ_TIMER, &clps7500_timer_irq);
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}
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static struct sys_timer clps7500_timer = {
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.init = clps7500_timer_init,
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.offset = ioc_timer_gettimeoffset,
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};
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static struct plat_serial8250_port serial_platform_data[] = {
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{
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.mapbase = 0x03010fe0,
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.irq = 10,
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.uartclk = 1843200,
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.regshift = 2,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST,
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},
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{
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.mapbase = 0x03010be0,
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.irq = 0,
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.uartclk = 1843200,
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.regshift = 2,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST,
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},
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{
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.iobase = ISASLOT_IO + 0x2e8,
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.irq = 41,
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.uartclk = 1843200,
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.regshift = 0,
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.iotype = UPIO_PORT,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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},
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{
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.iobase = ISASLOT_IO + 0x3e8,
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.irq = 40,
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.uartclk = 1843200,
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.regshift = 0,
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.iotype = UPIO_PORT,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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},
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{ },
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};
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static struct platform_device serial_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = serial_platform_data,
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},
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};
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static void __init clps7500_init(void)
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{
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platform_device_register(&serial_device);
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}
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MACHINE_START(CLPS7500, "CL-PS7500")
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/* Maintainer: Philip Blundell */
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.phys_ram = 0x10000000,
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.phys_io = 0x03000000,
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.io_pg_offst = ((0xe0000000) >> 18) & 0xfffc,
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.map_io = clps7500_map_io,
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.init_irq = clps7500_init_irq,
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.init_machine = clps7500_init,
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.timer = &clps7500_timer,
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MACHINE_END
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