linux/drivers/cxl
Terry Bowman d076bb8c4c cxl/pci: Refactor component register discovery for reuse
The endpoint implements component register setup code. Refactor it for
reuse with RCRB, downstream port, and upstream port setup.

Move PCI specifics from cxl_setup_regs() into cxl_pci_setup_regs().

Move cxl_setup_regs() into cxl/core/regs.c and export it. This also
includes supporting static functions cxl_map_registerblock(),
cxl_unmap_register_block() and cxl_probe_regs().

Co-developed-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20230622205523.85375-8-terry.bowman@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2023-06-25 11:39:38 -07:00
..
core cxl/pci: Refactor component register discovery for reuse 2023-06-25 11:39:38 -07:00
acpi.c cxl/acpi: Probe RCRB later during RCH downstream port creation 2023-06-25 11:35:20 -07:00
cxl.h cxl/pci: Refactor component register discovery for reuse 2023-06-25 11:39:38 -07:00
cxlmem.h cxl: Rename 'uport' to 'uport_dev' 2023-06-25 11:37:54 -07:00
cxlpci.h cxl: Wait Memory_Info_Valid before access memory related info 2023-05-18 16:42:41 -07:00
Kconfig Merge branch 'for-6.3/cxl-ram-region' into cxl/next 2023-02-10 18:11:01 -08:00
Makefile cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operation 2022-11-30 16:30:47 -08:00
mem.c cxl: Rename 'uport' to 'uport_dev' 2023-06-25 11:37:54 -07:00
pci.c cxl/pci: Refactor component register discovery for reuse 2023-06-25 11:39:38 -07:00
pmem.c cxl/pmem: Fix nvdimm registration races 2023-02-13 17:01:05 -08:00
port.c cxl: Rename 'uport' to 'uport_dev' 2023-06-25 11:37:54 -07:00
security.c cxl/mbox: Enable cxl_mbox_send_cmd() users to validate output size 2022-12-06 14:36:02 -08:00