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Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
83 lines
1.8 KiB
C
83 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
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*/
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#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H
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#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H
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/* MPUMODRST */
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#define CPU0_RESET 0
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#define CPU1_RESET 1
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#define WDS_RESET 2
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#define SCUPER_RESET 3
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#define L2_RESET 4
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/* PERMODRST */
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#define EMAC0_RESET 32
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#define EMAC1_RESET 33
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#define USB0_RESET 34
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#define USB1_RESET 35
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#define NAND_RESET 36
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#define QSPI_RESET 37
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#define L4WD0_RESET 38
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#define L4WD1_RESET 39
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#define OSC1TIMER0_RESET 40
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#define OSC1TIMER1_RESET 41
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#define SPTIMER0_RESET 42
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#define SPTIMER1_RESET 43
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#define I2C0_RESET 44
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#define I2C1_RESET 45
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#define I2C2_RESET 46
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#define I2C3_RESET 47
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#define UART0_RESET 48
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#define UART1_RESET 49
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#define SPIM0_RESET 50
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#define SPIM1_RESET 51
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#define SPIS0_RESET 52
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#define SPIS1_RESET 53
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#define SDMMC_RESET 54
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#define CAN0_RESET 55
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#define CAN1_RESET 56
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#define GPIO0_RESET 57
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#define GPIO1_RESET 58
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#define GPIO2_RESET 59
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#define DMA_RESET 60
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#define SDR_RESET 61
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/* PER2MODRST */
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#define DMAIF0_RESET 64
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#define DMAIF1_RESET 65
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#define DMAIF2_RESET 66
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#define DMAIF3_RESET 67
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#define DMAIF4_RESET 68
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#define DMAIF5_RESET 69
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#define DMAIF6_RESET 70
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#define DMAIF7_RESET 71
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/* BRGMODRST */
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#define HPS2FPGA_RESET 96
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#define LWHPS2FPGA_RESET 97
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#define FPGA2HPS_RESET 98
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/* MISCMODRST*/
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#define ROM_RESET 128
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#define OCRAM_RESET 129
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#define SYSMGR_RESET 130
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#define SYSMGRCOLD_RESET 131
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#define FPGAMGR_RESET 132
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#define ACPIDMAP_RESET 133
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#define S2F_RESET 134
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#define S2FCOLD_RESET 135
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#define NRSTPIN_RESET 136
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#define TIMESTAMPCOLD_RESET 137
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#define CLKMGRCOLD_RESET 138
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#define SCANMGR_RESET 139
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#define FRZCTRLCOLD_RESET 140
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#define SYSDBG_RESET 141
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#define DBG_RESET 142
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#define TAPCOLD_RESET 143
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#define SDRCOLD_RESET 144
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#endif
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