linux/arch/arm/mach-davinci/cp_intc.c
Linus Torvalds 50686e8a3a ARM: SoC platform updates for v4.3
New or improved SoC support:
 
 - Addition of support for Atmel's SAMA5D2 SoC
 - Addition of Freescale i.MX6UL
 - Improved support of TI's DM814x platform
 - Misc fixes and improvements for RockChip platforms
 - Marvell MVEBU suspend/resume support
 
 A few driver changes that ideally would belong in the drivers branch are
 also here (acked by appropriate maintainers):
 
 - Power key input driver for Freescale platforms (svns)
 - RTC driver updates for Freescale platforms (svns/mxc)
 - Clk fixes for TI DM814/816X
 
 + a bunch of other changes for various platforms
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJV5Mo6AAoJEIwa5zzehBx3VnMP/28LFJVUjIbd2xjJBo2gbSwV
 jN7uGlTkKU+1kHjZqnUPuirlBxBzsXKgRfBvCoeu0cPOggwmFcaF915/HHPz7xuz
 vTP7k98+Y5nSXScIohWkWCdZTpKKjve4sn74rXmiNakTUiuaHf5lKut/m7ldVrWd
 hN1o9W4LN+5O1mOYbc9ZD98v3bkDb6eu+a22oK7qemXiEiQi+NIMoDx+IR2bd4pA
 FeDaW7sOFWTEYU/p+M5nZNvI3n53P0/mlB5rPRiAYRjhQf9DrWHm5G7HdnMkUkgo
 /s8/QlVjBkJwhkY0TqpwtHY23JjSSB6UtCnXzb1eVAkX1nJN6PJQpcpCz1zJhd9q
 +sJ2k1zEvrfomJCK7/iZ1ubQE09KlJLEeb8xi5xCwD0MBOBAYC31bovDVAswCitV
 8NHnfltEG+wCMyX955eqqGkVxkcw8sJMJUK5A95aK6w+vKqjd7gUgLJjXFC1u4eN
 ECuVVUf1hVmUEmM799CDayTlfGDt4oGLmHGao+SiSCVc1XbG9HkWr7Lcgr6u9UHr
 lNv3RIe6Axb85xxIU0/9hqLHrtB85uEQjjlbnQx3o7u8RsSOeaiZvCz4BzcjP9E1
 VGyD6zkRWhuDiMFlPVXiAX0qIH5xSjIWkC0wPNJNy8eWFH9tkfGL0mOlLbl09oGR
 gtuvOrjbF/BhILkPw38y
 =8T5Z
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform updates from Olof Johansson:
 "New or improved SoC support:

   - add support for Atmel's SAMA5D2 SoC
   - add support for Freescale i.MX6UL
   - improved support for TI's DM814x platform
   - misc fixes and improvements for RockChip platforms
   - Marvell MVEBU suspend/resume support

  A few driver changes that ideally would belong in the drivers branch
  are also here (acked by appropriate maintainers):

   - power key input driver for Freescale platforms (svns)
   - RTC driver updates for Freescale platforms (svns/mxc)
   - clk fixes for TI DM814/816X

  + a bunch of other changes for various platforms"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits)
  ARM: rockchip: pm: Fix PTR_ERR() argument
  ARM: imx: mach-imx6ul: Fix allmodconfig build
  clk: ti: fix for definition movement
  ARM: uniphier: drop v7_invalidate_l1 call at secondary entry
  memory: kill off set_irq_flags usage
  rtc: snvs: select option REGMAP_MMIO
  ARM: brcmstb: select ARCH_DMA_ADDR_T_64BIT for LPAE
  ARM: BCM: Enable ARM erratum 798181 for BRCMSTB
  ARM: OMAP2+: Fix power domain operations regression caused by 81xx
  ARM: rockchip: enable PMU_GPIOINT_WAKEUP_EN when entering shallow suspend
  ARM: rockchip: set correct stabilization thresholds in suspend
  ARM: rockchip: rename osc_switch_to_32k variable
  ARM: imx6ul: add fec MAC refrence clock and phy fixup init
  ARM: imx6ul: add fec bits to GPR syscon definition
  rtc: mxc: add support of device tree
  dt-binding: document the binding for mxc rtc
  rtc: mxc: use a second rtc clock
  ARM: davinci: cp_intc: use IRQCHIP_SKIP_SET_WAKE instead of irq_set_wake callback
  soc: mediatek: Fix SCPSYS compilation
  ARM: at91/soc: add basic support for new sama5d2 SoC
  ...
2015-09-01 12:18:40 -07:00

213 lines
5.3 KiB
C

/*
* TI Common Platform Interrupt Controller (cp_intc) driver
*
* Author: Steve Chen <schen@mvista.com>
* Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <linux/export.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <mach/common.h>
#include <mach/cp_intc.h>
static inline unsigned int cp_intc_read(unsigned offset)
{
return __raw_readl(davinci_intc_base + offset);
}
static inline void cp_intc_write(unsigned long value, unsigned offset)
{
__raw_writel(value, davinci_intc_base + offset);
}
static void cp_intc_ack_irq(struct irq_data *d)
{
cp_intc_write(d->hwirq, CP_INTC_SYS_STAT_IDX_CLR);
}
/* Disable interrupt */
static void cp_intc_mask_irq(struct irq_data *d)
{
/* XXX don't know why we need to disable nIRQ here... */
cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_CLR);
cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
}
/* Enable interrupt */
static void cp_intc_unmask_irq(struct irq_data *d)
{
cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_SET);
}
static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type)
{
unsigned reg = BIT_WORD(d->hwirq);
unsigned mask = BIT_MASK(d->hwirq);
unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg));
unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg));
switch (flow_type) {
case IRQ_TYPE_EDGE_RISING:
polarity |= mask;
type |= mask;
break;
case IRQ_TYPE_EDGE_FALLING:
polarity &= ~mask;
type |= mask;
break;
case IRQ_TYPE_LEVEL_HIGH:
polarity |= mask;
type &= ~mask;
break;
case IRQ_TYPE_LEVEL_LOW:
polarity &= ~mask;
type &= ~mask;
break;
default:
return -EINVAL;
}
cp_intc_write(polarity, CP_INTC_SYS_POLARITY(reg));
cp_intc_write(type, CP_INTC_SYS_TYPE(reg));
return 0;
}
static struct irq_chip cp_intc_irq_chip = {
.name = "cp_intc",
.irq_ack = cp_intc_ack_irq,
.irq_mask = cp_intc_mask_irq,
.irq_unmask = cp_intc_unmask_irq,
.irq_set_type = cp_intc_set_irq_type,
.flags = IRQCHIP_SKIP_SET_WAKE,
};
static struct irq_domain *cp_intc_domain;
static int cp_intc_host_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
irq_set_chip(virq, &cp_intc_irq_chip);
irq_set_probe(virq);
irq_set_handler(virq, handle_edge_irq);
return 0;
}
static const struct irq_domain_ops cp_intc_host_ops = {
.map = cp_intc_host_map,
.xlate = irq_domain_xlate_onetwocell,
};
int __init cp_intc_of_init(struct device_node *node, struct device_node *parent)
{
u32 num_irq = davinci_soc_info.intc_irq_num;
u8 *irq_prio = davinci_soc_info.intc_irq_prios;
u32 *host_map = davinci_soc_info.intc_host_map;
unsigned num_reg = BITS_TO_LONGS(num_irq);
int i, irq_base;
davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;
if (node) {
davinci_intc_base = of_iomap(node, 0);
if (of_property_read_u32(node, "ti,intc-size", &num_irq))
pr_warn("unable to get intc-size, default to %d\n",
num_irq);
} else {
davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
}
if (WARN_ON(!davinci_intc_base))
return -EINVAL;
cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
/* Disable all host interrupts */
cp_intc_write(0, CP_INTC_HOST_ENABLE(0));
/* Disable system interrupts */
for (i = 0; i < num_reg; i++)
cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i));
/* Set to normal mode, no nesting, no priority hold */
cp_intc_write(0, CP_INTC_CTRL);
cp_intc_write(0, CP_INTC_HOST_CTRL);
/* Clear system interrupt status */
for (i = 0; i < num_reg; i++)
cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i));
/* Enable nIRQ (what about nFIQ?) */
cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
/*
* Priority is determined by host channel: lower channel number has
* higher priority i.e. channel 0 has highest priority and channel 31
* had the lowest priority.
*/
num_reg = (num_irq + 3) >> 2; /* 4 channels per register */
if (irq_prio) {
unsigned j, k;
u32 val;
for (k = i = 0; i < num_reg; i++) {
for (val = j = 0; j < 4; j++, k++) {
val >>= 8;
if (k < num_irq)
val |= irq_prio[k] << 24;
}
cp_intc_write(val, CP_INTC_CHAN_MAP(i));
}
} else {
/*
* Default everything to channel 15 if priority not specified.
* Note that channel 0-1 are mapped to nFIQ and channels 2-31
* are mapped to nIRQ.
*/
for (i = 0; i < num_reg; i++)
cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
}
if (host_map)
for (i = 0; host_map[i] != -1; i++)
cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));
irq_base = irq_alloc_descs(-1, 0, num_irq, 0);
if (irq_base < 0) {
pr_warn("Couldn't allocate IRQ numbers\n");
irq_base = 0;
}
/* create a legacy host */
cp_intc_domain = irq_domain_add_legacy(node, num_irq,
irq_base, 0, &cp_intc_host_ops, NULL);
if (!cp_intc_domain) {
pr_err("cp_intc: failed to allocate irq host!\n");
return -EINVAL;
}
/* Enable global interrupt */
cp_intc_write(1, CP_INTC_GLOBAL_ENABLE);
return 0;
}
void __init cp_intc_init(void)
{
cp_intc_of_init(NULL, NULL);
}