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3b5af9f116
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
352 lines
15 KiB
C
352 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* fsl_esai.h - ALSA ESAI interface for the Freescale i.MX SoC
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*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*
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* Author: Nicolin Chen <Guangyu.Chen@freescale.com>
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*/
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#ifndef _FSL_ESAI_DAI_H
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#define _FSL_ESAI_DAI_H
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/* ESAI Register Map */
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#define REG_ESAI_ETDR 0x00
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#define REG_ESAI_ERDR 0x04
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#define REG_ESAI_ECR 0x08
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#define REG_ESAI_ESR 0x0C
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#define REG_ESAI_TFCR 0x10
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#define REG_ESAI_TFSR 0x14
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#define REG_ESAI_RFCR 0x18
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#define REG_ESAI_RFSR 0x1C
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#define REG_ESAI_xFCR(tx) (tx ? REG_ESAI_TFCR : REG_ESAI_RFCR)
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#define REG_ESAI_xFSR(tx) (tx ? REG_ESAI_TFSR : REG_ESAI_RFSR)
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#define REG_ESAI_TX0 0x80
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#define REG_ESAI_TX1 0x84
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#define REG_ESAI_TX2 0x88
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#define REG_ESAI_TX3 0x8C
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#define REG_ESAI_TX4 0x90
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#define REG_ESAI_TX5 0x94
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#define REG_ESAI_TSR 0x98
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#define REG_ESAI_RX0 0xA0
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#define REG_ESAI_RX1 0xA4
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#define REG_ESAI_RX2 0xA8
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#define REG_ESAI_RX3 0xAC
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#define REG_ESAI_SAISR 0xCC
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#define REG_ESAI_SAICR 0xD0
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#define REG_ESAI_TCR 0xD4
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#define REG_ESAI_TCCR 0xD8
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#define REG_ESAI_RCR 0xDC
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#define REG_ESAI_RCCR 0xE0
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#define REG_ESAI_xCR(tx) (tx ? REG_ESAI_TCR : REG_ESAI_RCR)
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#define REG_ESAI_xCCR(tx) (tx ? REG_ESAI_TCCR : REG_ESAI_RCCR)
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#define REG_ESAI_TSMA 0xE4
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#define REG_ESAI_TSMB 0xE8
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#define REG_ESAI_RSMA 0xEC
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#define REG_ESAI_RSMB 0xF0
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#define REG_ESAI_xSMA(tx) (tx ? REG_ESAI_TSMA : REG_ESAI_RSMA)
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#define REG_ESAI_xSMB(tx) (tx ? REG_ESAI_TSMB : REG_ESAI_RSMB)
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#define REG_ESAI_PRRC 0xF8
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#define REG_ESAI_PCRC 0xFC
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/* ESAI Control Register -- REG_ESAI_ECR 0x8 */
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#define ESAI_ECR_ETI_SHIFT 19
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#define ESAI_ECR_ETI_MASK (1 << ESAI_ECR_ETI_SHIFT)
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#define ESAI_ECR_ETI (1 << ESAI_ECR_ETI_SHIFT)
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#define ESAI_ECR_ETO_SHIFT 18
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#define ESAI_ECR_ETO_MASK (1 << ESAI_ECR_ETO_SHIFT)
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#define ESAI_ECR_ETO (1 << ESAI_ECR_ETO_SHIFT)
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#define ESAI_ECR_ERI_SHIFT 17
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#define ESAI_ECR_ERI_MASK (1 << ESAI_ECR_ERI_SHIFT)
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#define ESAI_ECR_ERI (1 << ESAI_ECR_ERI_SHIFT)
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#define ESAI_ECR_ERO_SHIFT 16
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#define ESAI_ECR_ERO_MASK (1 << ESAI_ECR_ERO_SHIFT)
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#define ESAI_ECR_ERO (1 << ESAI_ECR_ERO_SHIFT)
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#define ESAI_ECR_ERST_SHIFT 1
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#define ESAI_ECR_ERST_MASK (1 << ESAI_ECR_ERST_SHIFT)
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#define ESAI_ECR_ERST (1 << ESAI_ECR_ERST_SHIFT)
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#define ESAI_ECR_ESAIEN_SHIFT 0
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#define ESAI_ECR_ESAIEN_MASK (1 << ESAI_ECR_ESAIEN_SHIFT)
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#define ESAI_ECR_ESAIEN (1 << ESAI_ECR_ESAIEN_SHIFT)
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/* ESAI Status Register -- REG_ESAI_ESR 0xC */
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#define ESAI_ESR_TINIT_SHIFT 10
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#define ESAI_ESR_TINIT_MASK (1 << ESAI_ESR_TINIT_SHIFT)
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#define ESAI_ESR_TINIT (1 << ESAI_ESR_TINIT_SHIFT)
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#define ESAI_ESR_RFF_SHIFT 9
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#define ESAI_ESR_RFF_MASK (1 << ESAI_ESR_RFF_SHIFT)
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#define ESAI_ESR_RFF (1 << ESAI_ESR_RFF_SHIFT)
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#define ESAI_ESR_TFE_SHIFT 8
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#define ESAI_ESR_TFE_MASK (1 << ESAI_ESR_TFE_SHIFT)
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#define ESAI_ESR_TFE (1 << ESAI_ESR_TFE_SHIFT)
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#define ESAI_ESR_TLS_SHIFT 7
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#define ESAI_ESR_TLS_MASK (1 << ESAI_ESR_TLS_SHIFT)
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#define ESAI_ESR_TLS (1 << ESAI_ESR_TLS_SHIFT)
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#define ESAI_ESR_TDE_SHIFT 6
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#define ESAI_ESR_TDE_MASK (1 << ESAI_ESR_TDE_SHIFT)
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#define ESAI_ESR_TDE (1 << ESAI_ESR_TDE_SHIFT)
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#define ESAI_ESR_TED_SHIFT 5
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#define ESAI_ESR_TED_MASK (1 << ESAI_ESR_TED_SHIFT)
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#define ESAI_ESR_TED (1 << ESAI_ESR_TED_SHIFT)
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#define ESAI_ESR_TD_SHIFT 4
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#define ESAI_ESR_TD_MASK (1 << ESAI_ESR_TD_SHIFT)
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#define ESAI_ESR_TD (1 << ESAI_ESR_TD_SHIFT)
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#define ESAI_ESR_RLS_SHIFT 3
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#define ESAI_ESR_RLS_MASK (1 << ESAI_ESR_RLS_SHIFT)
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#define ESAI_ESR_RLS (1 << ESAI_ESR_RLS_SHIFT)
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#define ESAI_ESR_RDE_SHIFT 2
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#define ESAI_ESR_RDE_MASK (1 << ESAI_ESR_RDE_SHIFT)
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#define ESAI_ESR_RDE (1 << ESAI_ESR_RDE_SHIFT)
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#define ESAI_ESR_RED_SHIFT 1
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#define ESAI_ESR_RED_MASK (1 << ESAI_ESR_RED_SHIFT)
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#define ESAI_ESR_RED (1 << ESAI_ESR_RED_SHIFT)
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#define ESAI_ESR_RD_SHIFT 0
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#define ESAI_ESR_RD_MASK (1 << ESAI_ESR_RD_SHIFT)
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#define ESAI_ESR_RD (1 << ESAI_ESR_RD_SHIFT)
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/*
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* Transmit FIFO Configuration Register -- REG_ESAI_TFCR 0x10
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* Receive FIFO Configuration Register -- REG_ESAI_RFCR 0x18
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*/
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#define ESAI_xFCR_TIEN_SHIFT 19
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#define ESAI_xFCR_TIEN_MASK (1 << ESAI_xFCR_TIEN_SHIFT)
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#define ESAI_xFCR_TIEN (1 << ESAI_xFCR_TIEN_SHIFT)
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#define ESAI_xFCR_REXT_SHIFT 19
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#define ESAI_xFCR_REXT_MASK (1 << ESAI_xFCR_REXT_SHIFT)
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#define ESAI_xFCR_REXT (1 << ESAI_xFCR_REXT_SHIFT)
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#define ESAI_xFCR_xWA_SHIFT 16
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#define ESAI_xFCR_xWA_WIDTH 3
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#define ESAI_xFCR_xWA_MASK (((1 << ESAI_xFCR_xWA_WIDTH) - 1) << ESAI_xFCR_xWA_SHIFT)
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#define ESAI_xFCR_xWA(v) (((8 - ((v) >> 2)) << ESAI_xFCR_xWA_SHIFT) & ESAI_xFCR_xWA_MASK)
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#define ESAI_xFCR_xFWM_SHIFT 8
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#define ESAI_xFCR_xFWM_WIDTH 8
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#define ESAI_xFCR_xFWM_MASK (((1 << ESAI_xFCR_xFWM_WIDTH) - 1) << ESAI_xFCR_xFWM_SHIFT)
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#define ESAI_xFCR_xFWM(v) ((((v) - 1) << ESAI_xFCR_xFWM_SHIFT) & ESAI_xFCR_xFWM_MASK)
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#define ESAI_xFCR_xE_SHIFT 2
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#define ESAI_xFCR_TE_WIDTH 6
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#define ESAI_xFCR_RE_WIDTH 4
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#define ESAI_xFCR_TE_MASK (((1 << ESAI_xFCR_TE_WIDTH) - 1) << ESAI_xFCR_xE_SHIFT)
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#define ESAI_xFCR_RE_MASK (((1 << ESAI_xFCR_RE_WIDTH) - 1) << ESAI_xFCR_xE_SHIFT)
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#define ESAI_xFCR_TE(x) ((ESAI_xFCR_TE_MASK >> (ESAI_xFCR_TE_WIDTH - x)) & ESAI_xFCR_TE_MASK)
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#define ESAI_xFCR_RE(x) ((ESAI_xFCR_RE_MASK >> (ESAI_xFCR_RE_WIDTH - x)) & ESAI_xFCR_RE_MASK)
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#define ESAI_xFCR_xFR_SHIFT 1
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#define ESAI_xFCR_xFR_MASK (1 << ESAI_xFCR_xFR_SHIFT)
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#define ESAI_xFCR_xFR (1 << ESAI_xFCR_xFR_SHIFT)
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#define ESAI_xFCR_xFEN_SHIFT 0
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#define ESAI_xFCR_xFEN_MASK (1 << ESAI_xFCR_xFEN_SHIFT)
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#define ESAI_xFCR_xFEN (1 << ESAI_xFCR_xFEN_SHIFT)
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/*
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* Transmit FIFO Status Register -- REG_ESAI_TFSR 0x14
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* Receive FIFO Status Register --REG_ESAI_RFSR 0x1C
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*/
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#define ESAI_xFSR_NTFO_SHIFT 12
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#define ESAI_xFSR_NRFI_SHIFT 12
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#define ESAI_xFSR_NTFI_SHIFT 8
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#define ESAI_xFSR_NRFO_SHIFT 8
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#define ESAI_xFSR_NTFx_WIDTH 3
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#define ESAI_xFSR_NRFx_WIDTH 2
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#define ESAI_xFSR_NTFO_MASK (((1 << ESAI_xFSR_NTFx_WIDTH) - 1) << ESAI_xFSR_NTFO_SHIFT)
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#define ESAI_xFSR_NTFI_MASK (((1 << ESAI_xFSR_NTFx_WIDTH) - 1) << ESAI_xFSR_NTFI_SHIFT)
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#define ESAI_xFSR_NRFO_MASK (((1 << ESAI_xFSR_NRFx_WIDTH) - 1) << ESAI_xFSR_NRFO_SHIFT)
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#define ESAI_xFSR_NRFI_MASK (((1 << ESAI_xFSR_NRFx_WIDTH) - 1) << ESAI_xFSR_NRFI_SHIFT)
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#define ESAI_xFSR_xFCNT_SHIFT 0
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#define ESAI_xFSR_xFCNT_WIDTH 8
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#define ESAI_xFSR_xFCNT_MASK (((1 << ESAI_xFSR_xFCNT_WIDTH) - 1) << ESAI_xFSR_xFCNT_SHIFT)
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/* ESAI Transmit Slot Register -- REG_ESAI_TSR 0x98 */
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#define ESAI_TSR_SHIFT 0
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#define ESAI_TSR_WIDTH 24
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#define ESAI_TSR_MASK (((1 << ESAI_TSR_WIDTH) - 1) << ESAI_TSR_SHIFT)
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/* Serial Audio Interface Status Register -- REG_ESAI_SAISR 0xCC */
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#define ESAI_SAISR_TODFE_SHIFT 17
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#define ESAI_SAISR_TODFE_MASK (1 << ESAI_SAISR_TODFE_SHIFT)
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#define ESAI_SAISR_TODFE (1 << ESAI_SAISR_TODFE_SHIFT)
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#define ESAI_SAISR_TEDE_SHIFT 16
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#define ESAI_SAISR_TEDE_MASK (1 << ESAI_SAISR_TEDE_SHIFT)
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#define ESAI_SAISR_TEDE (1 << ESAI_SAISR_TEDE_SHIFT)
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#define ESAI_SAISR_TDE_SHIFT 15
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#define ESAI_SAISR_TDE_MASK (1 << ESAI_SAISR_TDE_SHIFT)
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#define ESAI_SAISR_TDE (1 << ESAI_SAISR_TDE_SHIFT)
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#define ESAI_SAISR_TUE_SHIFT 14
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#define ESAI_SAISR_TUE_MASK (1 << ESAI_SAISR_TUE_SHIFT)
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#define ESAI_SAISR_TUE (1 << ESAI_SAISR_TUE_SHIFT)
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#define ESAI_SAISR_TFS_SHIFT 13
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#define ESAI_SAISR_TFS_MASK (1 << ESAI_SAISR_TFS_SHIFT)
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#define ESAI_SAISR_TFS (1 << ESAI_SAISR_TFS_SHIFT)
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#define ESAI_SAISR_RODF_SHIFT 10
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#define ESAI_SAISR_RODF_MASK (1 << ESAI_SAISR_RODF_SHIFT)
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#define ESAI_SAISR_RODF (1 << ESAI_SAISR_RODF_SHIFT)
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#define ESAI_SAISR_REDF_SHIFT 9
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#define ESAI_SAISR_REDF_MASK (1 << ESAI_SAISR_REDF_SHIFT)
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#define ESAI_SAISR_REDF (1 << ESAI_SAISR_REDF_SHIFT)
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#define ESAI_SAISR_RDF_SHIFT 8
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#define ESAI_SAISR_RDF_MASK (1 << ESAI_SAISR_RDF_SHIFT)
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#define ESAI_SAISR_RDF (1 << ESAI_SAISR_RDF_SHIFT)
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#define ESAI_SAISR_ROE_SHIFT 7
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#define ESAI_SAISR_ROE_MASK (1 << ESAI_SAISR_ROE_SHIFT)
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#define ESAI_SAISR_ROE (1 << ESAI_SAISR_ROE_SHIFT)
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#define ESAI_SAISR_RFS_SHIFT 6
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#define ESAI_SAISR_RFS_MASK (1 << ESAI_SAISR_RFS_SHIFT)
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#define ESAI_SAISR_RFS (1 << ESAI_SAISR_RFS_SHIFT)
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#define ESAI_SAISR_IF2_SHIFT 2
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#define ESAI_SAISR_IF2_MASK (1 << ESAI_SAISR_IF2_SHIFT)
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#define ESAI_SAISR_IF2 (1 << ESAI_SAISR_IF2_SHIFT)
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#define ESAI_SAISR_IF1_SHIFT 1
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#define ESAI_SAISR_IF1_MASK (1 << ESAI_SAISR_IF1_SHIFT)
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#define ESAI_SAISR_IF1 (1 << ESAI_SAISR_IF1_SHIFT)
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#define ESAI_SAISR_IF0_SHIFT 0
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#define ESAI_SAISR_IF0_MASK (1 << ESAI_SAISR_IF0_SHIFT)
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#define ESAI_SAISR_IF0 (1 << ESAI_SAISR_IF0_SHIFT)
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/* Serial Audio Interface Control Register -- REG_ESAI_SAICR 0xD0 */
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#define ESAI_SAICR_ALC_SHIFT 8
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#define ESAI_SAICR_ALC_MASK (1 << ESAI_SAICR_ALC_SHIFT)
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#define ESAI_SAICR_ALC (1 << ESAI_SAICR_ALC_SHIFT)
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#define ESAI_SAICR_TEBE_SHIFT 7
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#define ESAI_SAICR_TEBE_MASK (1 << ESAI_SAICR_TEBE_SHIFT)
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#define ESAI_SAICR_TEBE (1 << ESAI_SAICR_TEBE_SHIFT)
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#define ESAI_SAICR_SYNC_SHIFT 6
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#define ESAI_SAICR_SYNC_MASK (1 << ESAI_SAICR_SYNC_SHIFT)
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#define ESAI_SAICR_SYNC (1 << ESAI_SAICR_SYNC_SHIFT)
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#define ESAI_SAICR_OF2_SHIFT 2
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#define ESAI_SAICR_OF2_MASK (1 << ESAI_SAICR_OF2_SHIFT)
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#define ESAI_SAICR_OF2 (1 << ESAI_SAICR_OF2_SHIFT)
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#define ESAI_SAICR_OF1_SHIFT 1
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#define ESAI_SAICR_OF1_MASK (1 << ESAI_SAICR_OF1_SHIFT)
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#define ESAI_SAICR_OF1 (1 << ESAI_SAICR_OF1_SHIFT)
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#define ESAI_SAICR_OF0_SHIFT 0
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#define ESAI_SAICR_OF0_MASK (1 << ESAI_SAICR_OF0_SHIFT)
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#define ESAI_SAICR_OF0 (1 << ESAI_SAICR_OF0_SHIFT)
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/*
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* Transmit Control Register -- REG_ESAI_TCR 0xD4
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* Receive Control Register -- REG_ESAI_RCR 0xDC
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*/
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#define ESAI_xCR_xLIE_SHIFT 23
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#define ESAI_xCR_xLIE_MASK (1 << ESAI_xCR_xLIE_SHIFT)
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#define ESAI_xCR_xLIE (1 << ESAI_xCR_xLIE_SHIFT)
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#define ESAI_xCR_xIE_SHIFT 22
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#define ESAI_xCR_xIE_MASK (1 << ESAI_xCR_xIE_SHIFT)
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#define ESAI_xCR_xIE (1 << ESAI_xCR_xIE_SHIFT)
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#define ESAI_xCR_xEDIE_SHIFT 21
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#define ESAI_xCR_xEDIE_MASK (1 << ESAI_xCR_xEDIE_SHIFT)
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#define ESAI_xCR_xEDIE (1 << ESAI_xCR_xEDIE_SHIFT)
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#define ESAI_xCR_xEIE_SHIFT 20
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#define ESAI_xCR_xEIE_MASK (1 << ESAI_xCR_xEIE_SHIFT)
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#define ESAI_xCR_xEIE (1 << ESAI_xCR_xEIE_SHIFT)
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#define ESAI_xCR_xPR_SHIFT 19
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#define ESAI_xCR_xPR_MASK (1 << ESAI_xCR_xPR_SHIFT)
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#define ESAI_xCR_xPR (1 << ESAI_xCR_xPR_SHIFT)
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#define ESAI_xCR_PADC_SHIFT 17
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#define ESAI_xCR_PADC_MASK (1 << ESAI_xCR_PADC_SHIFT)
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#define ESAI_xCR_PADC (1 << ESAI_xCR_PADC_SHIFT)
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#define ESAI_xCR_xFSR_SHIFT 16
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#define ESAI_xCR_xFSR_MASK (1 << ESAI_xCR_xFSR_SHIFT)
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#define ESAI_xCR_xFSR (1 << ESAI_xCR_xFSR_SHIFT)
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#define ESAI_xCR_xFSL_SHIFT 15
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#define ESAI_xCR_xFSL_MASK (1 << ESAI_xCR_xFSL_SHIFT)
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#define ESAI_xCR_xFSL (1 << ESAI_xCR_xFSL_SHIFT)
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#define ESAI_xCR_xSWS_SHIFT 10
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#define ESAI_xCR_xSWS_WIDTH 5
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#define ESAI_xCR_xSWS_MASK (((1 << ESAI_xCR_xSWS_WIDTH) - 1) << ESAI_xCR_xSWS_SHIFT)
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#define ESAI_xCR_xSWS(s, w) ((w < 24 ? (s - w + ((w - 8) >> 2)) : (s < 32 ? 0x1e : 0x1f)) << ESAI_xCR_xSWS_SHIFT)
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#define ESAI_xCR_xMOD_SHIFT 8
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#define ESAI_xCR_xMOD_WIDTH 2
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#define ESAI_xCR_xMOD_MASK (((1 << ESAI_xCR_xMOD_WIDTH) - 1) << ESAI_xCR_xMOD_SHIFT)
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#define ESAI_xCR_xMOD_ONDEMAND (0x1 << ESAI_xCR_xMOD_SHIFT)
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#define ESAI_xCR_xMOD_NETWORK (0x1 << ESAI_xCR_xMOD_SHIFT)
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#define ESAI_xCR_xMOD_AC97 (0x3 << ESAI_xCR_xMOD_SHIFT)
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#define ESAI_xCR_xWA_SHIFT 7
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#define ESAI_xCR_xWA_MASK (1 << ESAI_xCR_xWA_SHIFT)
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#define ESAI_xCR_xWA (1 << ESAI_xCR_xWA_SHIFT)
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#define ESAI_xCR_xSHFD_SHIFT 6
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#define ESAI_xCR_xSHFD_MASK (1 << ESAI_xCR_xSHFD_SHIFT)
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#define ESAI_xCR_xSHFD (1 << ESAI_xCR_xSHFD_SHIFT)
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#define ESAI_xCR_xE_SHIFT 0
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#define ESAI_xCR_TE_WIDTH 6
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#define ESAI_xCR_RE_WIDTH 4
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#define ESAI_xCR_TE_MASK (((1 << ESAI_xCR_TE_WIDTH) - 1) << ESAI_xCR_xE_SHIFT)
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#define ESAI_xCR_RE_MASK (((1 << ESAI_xCR_RE_WIDTH) - 1) << ESAI_xCR_xE_SHIFT)
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#define ESAI_xCR_TE(x) ((ESAI_xCR_TE_MASK >> (ESAI_xCR_TE_WIDTH - x)) & ESAI_xCR_TE_MASK)
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#define ESAI_xCR_RE(x) ((ESAI_xCR_RE_MASK >> (ESAI_xCR_RE_WIDTH - x)) & ESAI_xCR_RE_MASK)
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/*
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* Transmit Clock Control Register -- REG_ESAI_TCCR 0xD8
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* Receive Clock Control Register -- REG_ESAI_RCCR 0xE0
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*/
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#define ESAI_xCCR_xHCKD_SHIFT 23
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#define ESAI_xCCR_xHCKD_MASK (1 << ESAI_xCCR_xHCKD_SHIFT)
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#define ESAI_xCCR_xHCKD (1 << ESAI_xCCR_xHCKD_SHIFT)
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#define ESAI_xCCR_xFSD_SHIFT 22
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#define ESAI_xCCR_xFSD_MASK (1 << ESAI_xCCR_xFSD_SHIFT)
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#define ESAI_xCCR_xFSD (1 << ESAI_xCCR_xFSD_SHIFT)
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#define ESAI_xCCR_xCKD_SHIFT 21
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#define ESAI_xCCR_xCKD_MASK (1 << ESAI_xCCR_xCKD_SHIFT)
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#define ESAI_xCCR_xCKD (1 << ESAI_xCCR_xCKD_SHIFT)
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#define ESAI_xCCR_xHCKP_SHIFT 20
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#define ESAI_xCCR_xHCKP_MASK (1 << ESAI_xCCR_xHCKP_SHIFT)
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#define ESAI_xCCR_xHCKP (1 << ESAI_xCCR_xHCKP_SHIFT)
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#define ESAI_xCCR_xFSP_SHIFT 19
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#define ESAI_xCCR_xFSP_MASK (1 << ESAI_xCCR_xFSP_SHIFT)
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#define ESAI_xCCR_xFSP (1 << ESAI_xCCR_xFSP_SHIFT)
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#define ESAI_xCCR_xCKP_SHIFT 18
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#define ESAI_xCCR_xCKP_MASK (1 << ESAI_xCCR_xCKP_SHIFT)
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#define ESAI_xCCR_xCKP (1 << ESAI_xCCR_xCKP_SHIFT)
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#define ESAI_xCCR_xFP_SHIFT 14
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#define ESAI_xCCR_xFP_WIDTH 4
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#define ESAI_xCCR_xFP_MASK (((1 << ESAI_xCCR_xFP_WIDTH) - 1) << ESAI_xCCR_xFP_SHIFT)
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#define ESAI_xCCR_xFP(v) ((((v) - 1) << ESAI_xCCR_xFP_SHIFT) & ESAI_xCCR_xFP_MASK)
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#define ESAI_xCCR_xDC_SHIFT 9
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#define ESAI_xCCR_xDC_WIDTH 5
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#define ESAI_xCCR_xDC_MASK (((1 << ESAI_xCCR_xDC_WIDTH) - 1) << ESAI_xCCR_xDC_SHIFT)
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#define ESAI_xCCR_xDC(v) ((((v) - 1) << ESAI_xCCR_xDC_SHIFT) & ESAI_xCCR_xDC_MASK)
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#define ESAI_xCCR_xPSR_SHIFT 8
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#define ESAI_xCCR_xPSR_MASK (1 << ESAI_xCCR_xPSR_SHIFT)
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#define ESAI_xCCR_xPSR_BYPASS (1 << ESAI_xCCR_xPSR_SHIFT)
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#define ESAI_xCCR_xPSR_DIV8 (0 << ESAI_xCCR_xPSR_SHIFT)
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#define ESAI_xCCR_xPM_SHIFT 0
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#define ESAI_xCCR_xPM_WIDTH 8
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#define ESAI_xCCR_xPM_MASK (((1 << ESAI_xCCR_xPM_WIDTH) - 1) << ESAI_xCCR_xPM_SHIFT)
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#define ESAI_xCCR_xPM(v) ((((v) - 1) << ESAI_xCCR_xPM_SHIFT) & ESAI_xCCR_xPM_MASK)
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/* Transmit Slot Mask Register A/B -- REG_ESAI_TSMA/B 0xE4 ~ 0xF0 */
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#define ESAI_xSMA_xS_SHIFT 0
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#define ESAI_xSMA_xS_WIDTH 16
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#define ESAI_xSMA_xS_MASK (((1 << ESAI_xSMA_xS_WIDTH) - 1) << ESAI_xSMA_xS_SHIFT)
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#define ESAI_xSMA_xS(v) ((v) & ESAI_xSMA_xS_MASK)
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#define ESAI_xSMB_xS_SHIFT 0
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#define ESAI_xSMB_xS_WIDTH 16
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#define ESAI_xSMB_xS_MASK (((1 << ESAI_xSMB_xS_WIDTH) - 1) << ESAI_xSMB_xS_SHIFT)
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#define ESAI_xSMB_xS(v) (((v) >> ESAI_xSMA_xS_WIDTH) & ESAI_xSMB_xS_MASK)
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/* Port C Direction Register -- REG_ESAI_PRRC 0xF8 */
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#define ESAI_PRRC_PDC_SHIFT 0
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#define ESAI_PRRC_PDC_WIDTH 12
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#define ESAI_PRRC_PDC_MASK (((1 << ESAI_PRRC_PDC_WIDTH) - 1) << ESAI_PRRC_PDC_SHIFT)
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#define ESAI_PRRC_PDC(v) ((v) & ESAI_PRRC_PDC_MASK)
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/* Port C Control Register -- REG_ESAI_PCRC 0xFC */
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#define ESAI_PCRC_PC_SHIFT 0
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#define ESAI_PCRC_PC_WIDTH 12
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#define ESAI_PCRC_PC_MASK (((1 << ESAI_PCRC_PC_WIDTH) - 1) << ESAI_PCRC_PC_SHIFT)
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#define ESAI_PCRC_PC(v) ((v) & ESAI_PCRC_PC_MASK)
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#define ESAI_GPIO 0xfff
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/* ESAI clock source */
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#define ESAI_HCKT_FSYS 0
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#define ESAI_HCKT_EXTAL 1
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#define ESAI_HCKR_FSYS 2
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#define ESAI_HCKR_EXTAL 3
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/* ESAI clock divider */
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#define ESAI_TX_DIV_PSR 0
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#define ESAI_TX_DIV_PM 1
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#define ESAI_TX_DIV_FP 2
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#define ESAI_RX_DIV_PSR 3
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#define ESAI_RX_DIV_PM 4
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#define ESAI_RX_DIV_FP 5
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#endif /* _FSL_ESAI_DAI_H */
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