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The SH7780 PCIC contains a read-only cache line size register that we can derive pci_cache_line_size from. So, make sure that the software idea of the cache line size actually matches the host controller's idea. Signed-off-by: Paul Mundt <lethal@linux-sh.org> |
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dma | ||
pci | ||
superhyway | ||
heartbeat.c | ||
Kconfig | ||
Makefile | ||
push-switch.c |