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13d2b4d11d
This fixes CVE-2013-0228 / XSA-42
Drew Jones while working on CVE-2013-0190 found that that unprivileged guest user
in 32bit PV guest can use to crash the > guest with the panic like this:
-------------
general protection fault: 0000 [#1] SMP
last sysfs file: /sys/devices/vbd-51712/block/xvda/dev
Modules linked in: sunrpc ipt_REJECT nf_conntrack_ipv4 nf_defrag_ipv4
iptable_filter ip_tables ip6t_REJECT nf_conntrack_ipv6 nf_defrag_ipv6
xt_state nf_conntrack ip6table_filter ip6_tables ipv6 xen_netfront ext4
mbcache jbd2 xen_blkfront dm_mirror dm_region_hash dm_log dm_mod [last
unloaded: scsi_wait_scan]
Pid: 1250, comm: r Not tainted 2.6.32-356.el6.i686 #1
EIP: 0061:[<c0407462>] EFLAGS: 00010086 CPU: 0
EIP is at xen_iret+0x12/0x2b
EAX: eb8d0000 EBX: 00000001 ECX: 08049860 EDX: 00000010
ESI: 00000000 EDI: 003d0f00 EBP: b77f8388
ESP: eb8d1fe0
DS: 0000 ES: 007b FS: 0000 GS: 00e0 SS: 0069
Process r (pid: 1250, ti=eb8d0000 task=c2953550 task.ti=eb8d0000)
Stack:
00000000 0027f416 00000073 00000206 b77f8364 0000007b 00000000 00000000
Call Trace:
Code: c3 8b 44 24 18 81 4c 24 38 00 02 00 00 8d 64 24 30 e9 03 00 00 00
8d 76 00 f7 44 24 08 00 00 02 80 75 33 50 b8 00 e0 ff ff 21 e0 <8b> 40
10 8b 04 85 a0 f6 ab c0 8b 80 0c b0 b3 c0 f6 44 24 0d 02
EIP: [<c0407462>] xen_iret+0x12/0x2b SS:ESP 0069:eb8d1fe0
general protection fault: 0000 [#2]
---[ end trace ab0d29a492dcd330 ]---
Kernel panic - not syncing: Fatal exception
Pid: 1250, comm: r Tainted: G D ---------------
2.6.32-356.el6.i686 #1
Call Trace:
[<c08476df>] ? panic+0x6e/0x122
[<c084b63c>] ? oops_end+0xbc/0xd0
[<c084b260>] ? do_general_protection+0x0/0x210
[<c084a9b7>] ? error_code+0x73/
-------------
Petr says: "
I've analysed the bug and I think that xen_iret() cannot cope with
mangled DS, in this case zeroed out (null selector/descriptor) by either
xen_failsafe_callback() or RESTORE_REGS because the corresponding LDT
entry was invalidated by the reproducer. "
Jan took a look at the preliminary patch and came up a fix that solves
this problem:
"This code gets called after all registers other than those handled by
IRET got already restored, hence a null selector in %ds or a non-null
one that got loaded from a code or read-only data descriptor would
cause a kernel mode fault (with the potential of crashing the kernel
as a whole, if panic_on_oops is set)."
The way to fix this is to realize that the we can only relay on the
registers that IRET restores. The two that are guaranteed are the
%cs and %ss as they are always fixed GDT selectors. Also they are
inaccessible from user mode - so they cannot be altered. This is
the approach taken in this patch.
Another alternative option suggested by Jan would be to relay on
the subtle realization that using the %ebp or %esp relative references uses
the %ss segment. In which case we could switch from using %eax to %ebp and
would not need the %ss over-rides. That would also require one extra
instruction to compensate for the one place where the register is used
as scaled index. However Andrew pointed out that is too subtle and if
further work was to be done in this code-path it could escape folks attention
and lead to accidents.
Reviewed-by: Petr Matousek <pmatouse@redhat.com>
Reported-by: Petr Matousek <pmatouse@redhat.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
229 lines
6.7 KiB
ArmAsm
229 lines
6.7 KiB
ArmAsm
/*
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* Asm versions of Xen pv-ops, suitable for either direct use or
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* inlining. The inline versions are the same as the direct-use
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* versions, with the pre- and post-amble chopped off.
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*
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* This code is encoded for size rather than absolute efficiency, with
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* a view to being able to inline as much as possible.
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*
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* We only bother with direct forms (ie, vcpu in pda) of the
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* operations here; the indirect forms are better handled in C, since
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* they're generally too large to inline anyway.
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*/
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#include <asm/thread_info.h>
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#include <asm/processor-flags.h>
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#include <asm/segment.h>
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#include <asm/asm.h>
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#include <xen/interface/xen.h>
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#include "xen-asm.h"
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/*
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* Force an event check by making a hypercall, but preserve regs
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* before making the call.
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*/
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check_events:
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push %eax
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push %ecx
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push %edx
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call xen_force_evtchn_callback
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pop %edx
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pop %ecx
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pop %eax
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ret
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/*
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* We can't use sysexit directly, because we're not running in ring0.
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* But we can easily fake it up using iret. Assuming xen_sysexit is
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* jumped to with a standard stack frame, we can just strip it back to
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* a standard iret frame and use iret.
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*/
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ENTRY(xen_sysexit)
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movl PT_EAX(%esp), %eax /* Shouldn't be necessary? */
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orl $X86_EFLAGS_IF, PT_EFLAGS(%esp)
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lea PT_EIP(%esp), %esp
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jmp xen_iret
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ENDPROC(xen_sysexit)
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/*
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* This is run where a normal iret would be run, with the same stack setup:
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* 8: eflags
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* 4: cs
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* esp-> 0: eip
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*
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* This attempts to make sure that any pending events are dealt with
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* on return to usermode, but there is a small window in which an
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* event can happen just before entering usermode. If the nested
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* interrupt ends up setting one of the TIF_WORK_MASK pending work
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* flags, they will not be tested again before returning to
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* usermode. This means that a process can end up with pending work,
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* which will be unprocessed until the process enters and leaves the
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* kernel again, which could be an unbounded amount of time. This
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* means that a pending signal or reschedule event could be
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* indefinitely delayed.
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*
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* The fix is to notice a nested interrupt in the critical window, and
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* if one occurs, then fold the nested interrupt into the current
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* interrupt stack frame, and re-process it iteratively rather than
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* recursively. This means that it will exit via the normal path, and
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* all pending work will be dealt with appropriately.
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*
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* Because the nested interrupt handler needs to deal with the current
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* stack state in whatever form its in, we keep things simple by only
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* using a single register which is pushed/popped on the stack.
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*/
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ENTRY(xen_iret)
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/* test eflags for special cases */
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testl $(X86_EFLAGS_VM | XEN_EFLAGS_NMI), 8(%esp)
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jnz hyper_iret
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push %eax
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ESP_OFFSET=4 # bytes pushed onto stack
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/*
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* Store vcpu_info pointer for easy access. Do it this way to
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* avoid having to reload %fs
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*/
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#ifdef CONFIG_SMP
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GET_THREAD_INFO(%eax)
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movl %ss:TI_cpu(%eax), %eax
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movl %ss:__per_cpu_offset(,%eax,4), %eax
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mov %ss:xen_vcpu(%eax), %eax
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#else
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movl %ss:xen_vcpu, %eax
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#endif
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/* check IF state we're restoring */
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testb $X86_EFLAGS_IF>>8, 8+1+ESP_OFFSET(%esp)
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/*
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* Maybe enable events. Once this happens we could get a
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* recursive event, so the critical region starts immediately
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* afterwards. However, if that happens we don't end up
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* resuming the code, so we don't have to be worried about
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* being preempted to another CPU.
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*/
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setz %ss:XEN_vcpu_info_mask(%eax)
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xen_iret_start_crit:
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/* check for unmasked and pending */
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cmpw $0x0001, %ss:XEN_vcpu_info_pending(%eax)
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/*
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* If there's something pending, mask events again so we can
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* jump back into xen_hypervisor_callback. Otherwise do not
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* touch XEN_vcpu_info_mask.
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*/
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jne 1f
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movb $1, %ss:XEN_vcpu_info_mask(%eax)
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1: popl %eax
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/*
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* From this point on the registers are restored and the stack
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* updated, so we don't need to worry about it if we're
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* preempted
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*/
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iret_restore_end:
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/*
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* Jump to hypervisor_callback after fixing up the stack.
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* Events are masked, so jumping out of the critical region is
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* OK.
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*/
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je xen_hypervisor_callback
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1: iret
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xen_iret_end_crit:
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_ASM_EXTABLE(1b, iret_exc)
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hyper_iret:
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/* put this out of line since its very rarely used */
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jmp hypercall_page + __HYPERVISOR_iret * 32
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.globl xen_iret_start_crit, xen_iret_end_crit
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/*
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* This is called by xen_hypervisor_callback in entry.S when it sees
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* that the EIP at the time of interrupt was between
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* xen_iret_start_crit and xen_iret_end_crit. We're passed the EIP in
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* %eax so we can do a more refined determination of what to do.
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*
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* The stack format at this point is:
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* ----------------
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* ss : (ss/esp may be present if we came from usermode)
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* esp :
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* eflags } outer exception info
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* cs }
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* eip }
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* ---------------- <- edi (copy dest)
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* eax : outer eax if it hasn't been restored
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* ----------------
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* eflags } nested exception info
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* cs } (no ss/esp because we're nested
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* eip } from the same ring)
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* orig_eax }<- esi (copy src)
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* - - - - - - - -
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* fs }
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* es }
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* ds } SAVE_ALL state
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* eax }
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* : :
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* ebx }<- esp
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* ----------------
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*
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* In order to deliver the nested exception properly, we need to shift
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* everything from the return addr up to the error code so it sits
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* just under the outer exception info. This means that when we
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* handle the exception, we do it in the context of the outer
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* exception rather than starting a new one.
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*
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* The only caveat is that if the outer eax hasn't been restored yet
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* (ie, it's still on stack), we need to insert its value into the
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* SAVE_ALL state before going on, since it's usermode state which we
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* eventually need to restore.
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*/
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ENTRY(xen_iret_crit_fixup)
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/*
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* Paranoia: Make sure we're really coming from kernel space.
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* One could imagine a case where userspace jumps into the
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* critical range address, but just before the CPU delivers a
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* GP, it decides to deliver an interrupt instead. Unlikely?
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* Definitely. Easy to avoid? Yes. The Intel documents
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* explicitly say that the reported EIP for a bad jump is the
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* jump instruction itself, not the destination, but some
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* virtual environments get this wrong.
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*/
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movl PT_CS(%esp), %ecx
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andl $SEGMENT_RPL_MASK, %ecx
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cmpl $USER_RPL, %ecx
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je 2f
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lea PT_ORIG_EAX(%esp), %esi
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lea PT_EFLAGS(%esp), %edi
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/*
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* If eip is before iret_restore_end then stack
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* hasn't been restored yet.
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*/
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cmp $iret_restore_end, %eax
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jae 1f
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movl 0+4(%edi), %eax /* copy EAX (just above top of frame) */
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movl %eax, PT_EAX(%esp)
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lea ESP_OFFSET(%edi), %edi /* move dest up over saved regs */
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/* set up the copy */
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1: std
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mov $PT_EIP / 4, %ecx /* saved regs up to orig_eax */
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rep movsl
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cld
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lea 4(%edi), %esp /* point esp to new frame */
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2: jmp xen_do_upcall
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