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c142f173cd
Add IRQ definitions for the VIC0 and VIC1 interrupts on the S3C6400 and S3C6410 SoCs. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
151 lines
5.1 KiB
C
151 lines
5.1 KiB
C
/* linux/arch/arm/plat-s3c64xx/include/mach/irqs.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX - Common IRQ support
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*/
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#ifndef __ASM_PLAT_S3C64XX_IRQS_H
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#define __ASM_PLAT_S3C64XX_IRQS_H __FILE__
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/* we keep the first set of CPU IRQs out of the range of
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* the ISA space, so that the PC104 has them to itself
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* and we don't end up having to do horrible things to the
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* standard ISA drivers....
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*
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* note, since we're using the VICs, our start must be a
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* mulitple of 32 to allow the common code to work
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*/
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#define S3C_IRQ_OFFSET (32)
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#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET)
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/* UART interrupts, each UART has 4 intterupts per channel so
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* use the space between the ISA and S3C main interrupts. Note, these
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* are not in the same order as the S3C24XX series! */
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#define IRQ_S3CUART_BASE0 (16)
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#define IRQ_S3CUART_BASE1 (20)
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#define IRQ_S3CUART_BASE2 (24)
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#define IRQ_S3CUART_BASE3 (28)
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#define UART_IRQ_RXD (0)
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#define UART_IRQ_ERR (1)
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#define UART_IRQ_TXD (2)
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#define UART_IRQ_MODEM (3)
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#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
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#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
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#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
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#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
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#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
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#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
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#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
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#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
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#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
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#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
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#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
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#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
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/* VIC based IRQs */
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#define S3C64XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x))
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#define S3C64XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x))
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/* VIC0 */
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#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0)
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#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1)
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#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2)
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#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3)
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#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4)
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#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5)
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#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6)
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#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6)
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#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7)
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#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8)
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#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8)
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#define IRQ_POST0 S3C64XX_IRQ_VIC0(9)
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#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10)
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#define IRQ_2D S3C64XX_IRQ_VIC0(11)
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#define IRQ_TVENC S3C64XX_IRQ_VIC0(12)
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#define IRQ_SCALER S3C64XX_IRQ_VIC0(13)
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#define IRQ_BATF S3C64XX_IRQ_VIC0(14)
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#define IRQ_JPEG S3C64XX_IRQ_VIC0(15)
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#define IRQ_MFC S3C64XX_IRQ_VIC0(16)
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#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17)
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#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18)
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#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19)
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#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20)
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#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21)
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#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22)
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#define IRQ_TIMER0 S3C64XX_IRQ_VIC0(23)
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#define IRQ_TIMER1 S3C64XX_IRQ_VIC0(24)
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#define IRQ_TIMER2 S3C64XX_IRQ_VIC0(25)
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#define IRQ_WDT S3C64XX_IRQ_VIC0(26)
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#define IRQ_TIMER3 S3C64XX_IRQ_VIC0(27)
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#define IRQ_TIMER4 S3C64XX_IRQ_VIC0(28)
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#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29)
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#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30)
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#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31)
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/* VIC1 */
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#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0)
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#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1)
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#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2)
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#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3)
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#define IRQ_AC97 S3C64XX_IRQ_VIC1(4)
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#define IRQ_UART0 S3C64XX_IRQ_VIC1(5)
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#define IRQ_UART1 S3C64XX_IRQ_VIC1(6)
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#define IRQ_UART2 S3C64XX_IRQ_VIC1(7)
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#define IRQ_UART3 S3C64XX_IRQ_VIC1(8)
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#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9)
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#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10)
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#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11)
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#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12)
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#define IRQ_NFC S3C64XX_IRQ_VIC1(13)
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#define IRQ_CFCON S3C64XX_IRQ_VIC1(14)
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#define IRQ_UHOST S3C64XX_IRQ_VIC1(15)
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#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16)
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#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17)
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#define IRQ_IIC S3C64XX_IRQ_VIC1(18)
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#define IRQ_HSItx S3C64XX_IRQ_VIC1(19)
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#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20)
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#define IRQ_RESERVED S3C64XX_IRQ_VIC1(21)
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#define IRQ_MSM S3C64XX_IRQ_VIC1(22)
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#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23)
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#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24)
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#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25)
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#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */
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#define IRQ_OTG S3C64XX_IRQ_VIC1(26)
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#define IRQ_IRDA S3C64XX_IRQ_VIC1(27)
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#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28)
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#define IRQ_SEC S3C64XX_IRQ_VIC1(29)
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#define IRQ_PENDN S3C64XX_IRQ_VIC1(30)
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#define IRQ_TC IRQ_PENDN
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#define IRQ_ADC S3C64XX_IRQ_VIC1(31)
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/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
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* we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
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* which we place after the pair of VICs. */
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#define S3C_IRQ_EINT_BASE S3C_IRQ(64)
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#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE)
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/* Define NR_IRQs here, machine specific can always re-define.
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* Currently the IRQ_EINT27 is the last one we can have. */
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#define NR_IRQS (S3C_EINT(27) + 1)
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#endif /* __ASM_PLAT_S3C64XX_IRQS_H */
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