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fa83c6f45a
Implement an ARM delay timer to be used for udelay(). This allows us to skip the delay loop calibration at boot. With this patch udelay() is now independent of CPU frequency changes. This is a good thing on Meson8, Meson8b and Meson8m2 because changing the CPU frequency requires running the CPU clock off the XTAL while changing the PLL or it's dividers. After changing the CPU clocks we need to wait a few usecs for the clock to become stable. So having an udelay() implementation that doesn't depend on the CPU frequency is beneficial. Suggested-by: Jianxin Pan <jianxin.pan@amlogic.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
221 lines
6.0 KiB
C
221 lines
6.0 KiB
C
/*
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* Amlogic Meson6 SoCs timer handling.
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*
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* Copyright (C) 2014 Carlo Caione <carlo@caione.org>
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*
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* Based on code from Amlogic, Inc
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqreturn.h>
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#include <linux/sched_clock.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#ifdef CONFIG_ARM
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#include <linux/delay.h>
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#endif
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#define MESON_ISA_TIMER_MUX 0x00
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#define MESON_ISA_TIMER_MUX_TIMERD_EN BIT(19)
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#define MESON_ISA_TIMER_MUX_TIMERC_EN BIT(18)
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#define MESON_ISA_TIMER_MUX_TIMERB_EN BIT(17)
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#define MESON_ISA_TIMER_MUX_TIMERA_EN BIT(16)
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#define MESON_ISA_TIMER_MUX_TIMERD_MODE BIT(15)
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#define MESON_ISA_TIMER_MUX_TIMERC_MODE BIT(14)
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#define MESON_ISA_TIMER_MUX_TIMERB_MODE BIT(13)
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#define MESON_ISA_TIMER_MUX_TIMERA_MODE BIT(12)
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#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK GENMASK(10, 8)
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#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_SYSTEM_CLOCK 0x0
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#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US 0x1
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#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_10US 0x2
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#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_100US 0x3
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#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1MS 0x4
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#define MESON_ISA_TIMER_MUX_TIMERD_INPUT_CLOCK_MASK GENMASK(7, 6)
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#define MESON_ISA_TIMER_MUX_TIMERC_INPUT_CLOCK_MASK GENMASK(5, 4)
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#define MESON_ISA_TIMER_MUX_TIMERB_INPUT_CLOCK_MASK GENMASK(3, 2)
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#define MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK GENMASK(1, 0)
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#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US 0x0
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#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_10US 0x1
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#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_100US 0x0
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#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1MS 0x3
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#define MESON_ISA_TIMERA 0x04
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#define MESON_ISA_TIMERB 0x08
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#define MESON_ISA_TIMERC 0x0c
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#define MESON_ISA_TIMERD 0x10
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#define MESON_ISA_TIMERE 0x14
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static void __iomem *timer_base;
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#ifdef CONFIG_ARM
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static unsigned long meson6_read_current_timer(void)
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{
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return readl_relaxed(timer_base + MESON_ISA_TIMERE);
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}
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static struct delay_timer meson6_delay_timer = {
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.read_current_timer = meson6_read_current_timer,
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.freq = 1000 * 1000,
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};
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#endif
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static u64 notrace meson6_timer_sched_read(void)
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{
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return (u64)readl(timer_base + MESON_ISA_TIMERE);
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}
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static void meson6_clkevt_time_stop(void)
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{
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u32 val = readl(timer_base + MESON_ISA_TIMER_MUX);
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writel(val & ~MESON_ISA_TIMER_MUX_TIMERA_EN,
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timer_base + MESON_ISA_TIMER_MUX);
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}
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static void meson6_clkevt_time_setup(unsigned long delay)
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{
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writel(delay, timer_base + MESON_ISA_TIMERA);
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}
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static void meson6_clkevt_time_start(bool periodic)
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{
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u32 val = readl(timer_base + MESON_ISA_TIMER_MUX);
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if (periodic)
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val |= MESON_ISA_TIMER_MUX_TIMERA_MODE;
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else
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val &= ~MESON_ISA_TIMER_MUX_TIMERA_MODE;
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writel(val | MESON_ISA_TIMER_MUX_TIMERA_EN,
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timer_base + MESON_ISA_TIMER_MUX);
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}
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static int meson6_shutdown(struct clock_event_device *evt)
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{
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meson6_clkevt_time_stop();
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return 0;
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}
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static int meson6_set_oneshot(struct clock_event_device *evt)
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{
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meson6_clkevt_time_stop();
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meson6_clkevt_time_start(false);
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return 0;
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}
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static int meson6_set_periodic(struct clock_event_device *evt)
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{
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meson6_clkevt_time_stop();
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meson6_clkevt_time_setup(USEC_PER_SEC / HZ - 1);
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meson6_clkevt_time_start(true);
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return 0;
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}
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static int meson6_clkevt_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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meson6_clkevt_time_stop();
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meson6_clkevt_time_setup(evt);
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meson6_clkevt_time_start(false);
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return 0;
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}
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static struct clock_event_device meson6_clockevent = {
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.name = "meson6_tick",
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.rating = 400,
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.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT,
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.set_state_shutdown = meson6_shutdown,
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.set_state_periodic = meson6_set_periodic,
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.set_state_oneshot = meson6_set_oneshot,
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.tick_resume = meson6_shutdown,
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.set_next_event = meson6_clkevt_next_event,
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};
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static irqreturn_t meson6_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction meson6_timer_irq = {
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.name = "meson6_timer",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = meson6_timer_interrupt,
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.dev_id = &meson6_clockevent,
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};
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static int __init meson6_timer_init(struct device_node *node)
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{
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u32 val;
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int ret, irq;
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timer_base = of_io_request_and_map(node, 0, "meson6-timer");
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if (IS_ERR(timer_base)) {
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pr_err("Can't map registers\n");
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return -ENXIO;
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}
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irq = irq_of_parse_and_map(node, 0);
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if (irq <= 0) {
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pr_err("Can't parse IRQ\n");
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return -EINVAL;
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}
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/* Set 1us for timer E */
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val = readl(timer_base + MESON_ISA_TIMER_MUX);
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val &= ~MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK;
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val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK,
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MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US);
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writel(val, timer_base + MESON_ISA_TIMER_MUX);
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sched_clock_register(meson6_timer_sched_read, 32, USEC_PER_SEC);
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clocksource_mmio_init(timer_base + MESON_ISA_TIMERE, node->name,
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1000 * 1000, 300, 32, clocksource_mmio_readl_up);
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/* Timer A base 1us */
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val &= ~MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK;
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val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK,
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MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US);
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writel(val, timer_base + MESON_ISA_TIMER_MUX);
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/* Stop the timer A */
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meson6_clkevt_time_stop();
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ret = setup_irq(irq, &meson6_timer_irq);
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if (ret) {
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pr_warn("failed to setup irq %d\n", irq);
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return ret;
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}
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meson6_clockevent.cpumask = cpu_possible_mask;
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meson6_clockevent.irq = irq;
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clockevents_config_and_register(&meson6_clockevent, USEC_PER_SEC,
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1, 0xfffe);
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#ifdef CONFIG_ARM
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/* Also use MESON_ISA_TIMERE for delays */
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register_current_timer_delay(&meson6_delay_timer);
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#endif
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return 0;
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}
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TIMER_OF_DECLARE(meson6, "amlogic,meson6-timer",
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meson6_timer_init);
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