Scott Telford bebbc4bcf3 xtensa: Tweak xuartps UART driver Rx watermark for Cadence CSP config. ... Add module parameter xilinx_uartps.rx_trigger_level=32 to command line options for CSP to set Rx watermark for xuartps driver lower than the default value, to avoid UART overruns at 115200 bps. Signed-off-by: Scott Telford <stelford@cadence.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>		2016-09-19 11:51:32 -07:00
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boot	xtensa: Tweak xuartps UART driver Rx watermark for Cadence CSP config.	2016-09-19 11:51:32 -07:00
configs	xtensa: Added Cadence CSP kernel configuration for Xtensa	2016-09-09 18:39:09 -07:00
include	xtensa: extract common CPU reset code into separate function	2016-09-11 23:53:22 -07:00
kernel	xtensa: initialize MMU before jumping to reset vector	2016-09-11 23:53:23 -07:00
lib	xtensa: fixes for configs without loop option	2015-11-02 18:02:47 +03:00
mm	xtensa: support reserved-memory DT node	2016-07-24 06:34:00 +03:00
oprofile	xtensa: move oprofile stack tracing to stacktrace.c	2015-08-17 07:32:49 +03:00
platforms	xtensa: extract common CPU reset code into separate function	2016-09-11 23:53:22 -07:00
variants	xtensa: Added Cadence CSP kernel configuration for Xtensa	2016-09-09 18:39:09 -07:00
Kconfig	xtensa: fix default kernel load address	2016-09-09 18:38:35 -07:00
Kconfig.debug	xtensa: disable link optimization	2014-12-15 23:47:24 -08:00
Makefile	xtensa: define CONFIG_CPU_{BIG,LITTLE}_ENDIAN	2016-03-11 08:53:31 +00:00