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d4b2bab4f2
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
288 lines
8.0 KiB
C
288 lines
8.0 KiB
C
/*
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* pata-cs5535.c - CS5535 PATA for new ATA layer
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* (C) 2005-2006 Red Hat Inc
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* Alan Cox <alan@redhat.com>
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*
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* based upon cs5535.c from AMD <Jens.Altmann@amd.com> as cleaned up and
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* made readable and Linux style by Wolfgang Zuleger <wolfgang.zuleger@gmx.de
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* and Alexander Kiausch <alex.kiausch@t-online.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Loosely based on the piix & svwks drivers.
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*
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* Documentation:
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* Available from AMD web site.
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* TODO
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* Review errata to see if serializing is neccessary
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include <asm/msr.h>
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#define DRV_NAME "cs5535"
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#define DRV_VERSION "0.2.11"
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/*
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* The Geode (Aka Athlon GX now) uses an internal MSR based
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* bus system for control. Demented but there you go.
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*/
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#define MSR_ATAC_BASE 0x51300000
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#define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0)
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#define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01)
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#define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02)
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#define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03)
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#define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04)
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#define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05)
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#define ATAC_IO_BAR (MSR_ATAC_BASE+0x08)
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#define ATAC_RESET (MSR_ATAC_BASE+0x10)
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#define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20)
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#define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21)
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#define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22)
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#define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23)
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#define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24)
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#define ATAC_BM0_CMD_PRIM 0x00
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#define ATAC_BM0_STS_PRIM 0x02
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#define ATAC_BM0_PRD 0x04
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#define CS5535_CABLE_DETECT 0x48
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#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL)==0x00009172 )
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/**
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* cs5535_cable_detect - detect cable type
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* @ap: Port to detect on
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* @deadline: deadline jiffies for the operation
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*
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* Perform cable detection for ATA66 capable cable. Return a libata
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* cable type.
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*/
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static int cs5535_cable_detect(struct ata_port *ap)
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{
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u8 cable;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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pci_read_config_byte(pdev, CS5535_CABLE_DETECT, &cable);
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if (cable & 1)
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return ATA_CBL_PATA80;
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else
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return ATA_CBL_PATA40;
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}
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/**
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* cs5535_set_piomode - PIO setup
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* @ap: ATA interface
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* @adev: device on the interface
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*
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* Set our PIO requirements. The CS5535 is pretty clean about all this
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*/
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static void cs5535_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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static const u16 pio_timings[5] = {
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0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
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};
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static const u16 pio_cmd_timings[5] = {
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0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131
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};
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u32 reg, dummy;
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struct ata_device *pair = ata_dev_pair(adev);
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int mode = adev->pio_mode - XFER_PIO_0;
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int cmdmode = mode;
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/* Command timing has to be for the lowest of the pair of devices */
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if (pair) {
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int pairmode = pair->pio_mode - XFER_PIO_0;
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cmdmode = min(mode, pairmode);
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/* Write the other drive timing register if it changed */
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if (cmdmode < pairmode)
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wrmsr(ATAC_CH0D0_PIO + 2 * pair->devno,
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pio_cmd_timings[cmdmode] << 16 | pio_timings[pairmode], 0);
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}
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/* Write the drive timing register */
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wrmsr(ATAC_CH0D0_PIO + 2 * adev->devno,
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pio_cmd_timings[cmdmode] << 16 | pio_timings[mode], 0);
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/* Set the PIO "format 1" bit in the DMA timing register */
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rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
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wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg | 0x80000000UL, 0);
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}
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/**
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* cs5535_set_dmamode - DMA timing setup
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* @ap: ATA interface
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* @adev: Device being configured
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*
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*/
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static void cs5535_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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static const u32 udma_timings[5] = {
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0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061
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};
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static const u32 mwdma_timings[3] = {
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0x7F0FFFF3, 0x7F035352, 0x7F024241
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};
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u32 reg, dummy;
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int mode = adev->dma_mode;
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rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy);
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reg &= 0x80000000UL;
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if (mode >= XFER_UDMA_0)
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reg |= udma_timings[mode - XFER_UDMA_0];
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else
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reg |= mwdma_timings[mode - XFER_MW_DMA_0];
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wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, 0);
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}
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static struct scsi_host_template cs5535_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.slave_destroy = ata_scsi_slave_destroy,
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.bios_param = ata_std_bios_param,
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#ifdef CONFIG_PM
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.resume = ata_scsi_device_resume,
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.suspend = ata_scsi_device_suspend,
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#endif
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};
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static struct ata_port_operations cs5535_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = cs5535_set_piomode,
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.set_dmamode = cs5535_set_dmamode,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = ata_bmdma_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.cable_detect = cs5535_cable_detect,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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.port_start = ata_port_start,
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};
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/**
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* cs5535_init_one - Initialise a CS5530
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* @dev: PCI device
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* @id: Entry in match table
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*
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* Install a driver for the newly found CS5530 companion chip. Most of
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* this is just housekeeping. We have to set the chip up correctly and
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* turn off various bits of emulation magic.
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*/
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static int cs5535_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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static struct ata_port_info info = {
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.sht = &cs5535_sht,
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.flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.udma_mask = 0x1f,
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.port_ops = &cs5535_port_ops
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};
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struct ata_port_info *ports[1] = { &info };
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u32 timings, dummy;
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/* Check the BIOS set the initial timing clock. If not set the
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timings for PIO0 */
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rdmsr(ATAC_CH0D0_PIO, timings, dummy);
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if (CS5535_BAD_PIO(timings))
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wrmsr(ATAC_CH0D0_PIO, 0xF7F4F7F4UL, 0);
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rdmsr(ATAC_CH0D1_PIO, timings, dummy);
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if (CS5535_BAD_PIO(timings))
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wrmsr(ATAC_CH0D1_PIO, 0xF7F4F7F4UL, 0);
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return ata_pci_init_one(dev, ports, 1);
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}
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static const struct pci_device_id cs5535[] = {
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{ PCI_VDEVICE(NS, 0x002D), },
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{ },
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};
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static struct pci_driver cs5535_pci_driver = {
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.name = DRV_NAME,
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.id_table = cs5535,
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.probe = cs5535_init_one,
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.remove = ata_pci_remove_one,
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#ifdef CONFIG_PM
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.suspend = ata_pci_device_suspend,
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.resume = ata_pci_device_resume,
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#endif
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};
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static int __init cs5535_init(void)
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{
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return pci_register_driver(&cs5535_pci_driver);
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}
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static void __exit cs5535_exit(void)
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{
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pci_unregister_driver(&cs5535_pci_driver);
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}
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MODULE_AUTHOR("Alan Cox, Jens Altmann, Wolfgan Zuleger, Alexander Kiausch");
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MODULE_DESCRIPTION("low-level driver for the NS/AMD 5530");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, cs5535);
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MODULE_VERSION(DRV_VERSION);
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module_init(cs5535_init);
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module_exit(cs5535_exit);
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