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Create a sub-driver for the FPGA Card BMC in order to support secure updates. This patch creates the Max10 BMC Secure Update driver and provides sysfs files for displaying the root entry hashes (REH) for the FPGA static region (SR), the FPGA Partial Reconfiguration (PR) region, and the card BMC. The Intel MAX10 BMC Root of Trust (RoT) requires that all BMC Nios firmware and FPGA images are authenticated using ECDSA before loading and executing on the card. Code Signing Keys (CSK) are used to sign images. CSKs are signed by a root key. The root entry hash is created from the root public key. The RoT provides authentication by storing an REH bitstream to a write-once location. Image signatures are verified against the hash. Reviewed-by: Tom Rix <trix@redhat.com> Tested-by: Tianfei Zhang <tianfei.zhang@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Link: https://lore.kernel.org/r/20220606160038.846236-3-russell.h.weight@intel.com Signed-off-by: Xu Yilun <yilun.xu@intel.com>
55 lines
2.0 KiB
Makefile
55 lines
2.0 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for the fpga framework and fpga manager drivers.
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#
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# Core FPGA Manager Framework
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obj-$(CONFIG_FPGA) += fpga-mgr.o
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# FPGA Manager Drivers
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obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o
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obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o
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obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
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obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o
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obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
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obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
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obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o
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obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
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obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
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obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
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obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
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obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o
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obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
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obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
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# FPGA Secure Update Drivers
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obj-$(CONFIG_FPGA_M10_BMC_SEC_UPDATE) += intel-m10-bmc-sec-update.o
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# FPGA Bridge Drivers
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obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
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obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o
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obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
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obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o
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# High Level Interfaces
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obj-$(CONFIG_FPGA_REGION) += fpga-region.o
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obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
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# FPGA Device Feature List Support
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obj-$(CONFIG_FPGA_DFL) += dfl.o
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obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o
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obj-$(CONFIG_FPGA_DFL_FME_MGR) += dfl-fme-mgr.o
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obj-$(CONFIG_FPGA_DFL_FME_BRIDGE) += dfl-fme-br.o
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obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o
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obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o
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dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o
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dfl-fme-objs += dfl-fme-perf.o
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dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o
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dfl-afu-objs += dfl-afu-error.o
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obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o
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# Drivers for FPGAs which implement DFL
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obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
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