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494e5b6fae
sparc: Resolve conflict between sparc v9 and M7 on usage of bit 9 of TTE Bit 9 of TTE is CV (Cacheable in V-cache) on sparc v9 processor while the same bit 9 is MCDE (Memory Corruption Detection Enable) on M7 processor. This creates a conflicting usage of the same bit. Kernel sets TTE.cv bit on all pages for sun4v architecture which works well for sparc v9 but enables memory corruption detection on M7 processor which is not the intent. This patch adds code to determine if kernel is running on M7 processor and takes steps to not enable memory corruption detection in TTE erroneously. Signed-off-by: Khalid Aziz <khalid.aziz@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
250 lines
8.6 KiB
C
250 lines
8.6 KiB
C
#ifndef _ENTRY_H
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#define _ENTRY_H
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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/* irq */
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void handler_irq(int irq, struct pt_regs *regs);
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#ifdef CONFIG_SPARC32
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/* traps */
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void do_hw_interrupt(struct pt_regs *regs, unsigned long type);
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void do_illegal_instruction(struct pt_regs *regs, unsigned long pc,
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unsigned long npc, unsigned long psr);
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void do_priv_instruction(struct pt_regs *regs, unsigned long pc,
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unsigned long npc, unsigned long psr);
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void do_memaccess_unaligned(struct pt_regs *regs, unsigned long pc,
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unsigned long npc, unsigned long psr);
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void do_fpd_trap(struct pt_regs *regs, unsigned long pc,
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unsigned long npc, unsigned long psr);
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void do_fpe_trap(struct pt_regs *regs, unsigned long pc,
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unsigned long npc, unsigned long psr);
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void handle_tag_overflow(struct pt_regs *regs, unsigned long pc,
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unsigned long npc, unsigned long psr);
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void handle_watchpoint(struct pt_regs *regs, unsigned long pc,
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unsigned long npc, unsigned long psr);
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void handle_reg_access(struct pt_regs *regs, unsigned long pc,
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unsigned long npc, unsigned long psr);
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void handle_cp_disabled(struct pt_regs *regs, unsigned long pc,
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unsigned long npc, unsigned long psr);
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void handle_cp_exception(struct pt_regs *regs, unsigned long pc,
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unsigned long npc, unsigned long psr);
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/* entry.S */
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void fpsave(unsigned long *fpregs, unsigned long *fsr,
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void *fpqueue, unsigned long *fpqdepth);
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void fpload(unsigned long *fpregs, unsigned long *fsr);
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#else /* CONFIG_SPARC32 */
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#include <asm/trap_block.h>
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struct popc_3insn_patch_entry {
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unsigned int addr;
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unsigned int insns[3];
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};
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extern struct popc_3insn_patch_entry __popc_3insn_patch,
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__popc_3insn_patch_end;
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struct popc_6insn_patch_entry {
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unsigned int addr;
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unsigned int insns[6];
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};
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extern struct popc_6insn_patch_entry __popc_6insn_patch,
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__popc_6insn_patch_end;
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struct pause_patch_entry {
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unsigned int addr;
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unsigned int insns[3];
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};
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extern struct pause_patch_entry __pause_3insn_patch,
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__pause_3insn_patch_end;
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void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *,
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struct sun4v_1insn_patch_entry *);
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void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *,
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struct sun4v_2insn_patch_entry *);
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void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *,
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struct sun4v_2insn_patch_entry *);
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extern unsigned int dcache_parity_tl1_occurred;
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extern unsigned int icache_parity_tl1_occurred;
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asmlinkage void sparc_breakpoint(struct pt_regs *regs);
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void timer_interrupt(int irq, struct pt_regs *regs);
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void do_notify_resume(struct pt_regs *regs,
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unsigned long orig_i0,
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unsigned long thread_info_flags);
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asmlinkage int syscall_trace_enter(struct pt_regs *regs);
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asmlinkage void syscall_trace_leave(struct pt_regs *regs);
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void bad_trap_tl1(struct pt_regs *regs, long lvl);
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void do_fpieee(struct pt_regs *regs);
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void do_fpother(struct pt_regs *regs);
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void do_tof(struct pt_regs *regs);
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void do_div0(struct pt_regs *regs);
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void do_illegal_instruction(struct pt_regs *regs);
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void mem_address_unaligned(struct pt_regs *regs,
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unsigned long sfar,
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unsigned long sfsr);
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void sun4v_do_mna(struct pt_regs *regs,
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unsigned long addr,
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unsigned long type_ctx);
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void do_privop(struct pt_regs *regs);
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void do_privact(struct pt_regs *regs);
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void do_cee(struct pt_regs *regs);
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void do_div0_tl1(struct pt_regs *regs);
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void do_fpieee_tl1(struct pt_regs *regs);
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void do_fpother_tl1(struct pt_regs *regs);
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void do_ill_tl1(struct pt_regs *regs);
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void do_irq_tl1(struct pt_regs *regs);
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void do_lddfmna_tl1(struct pt_regs *regs);
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void do_stdfmna_tl1(struct pt_regs *regs);
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void do_paw(struct pt_regs *regs);
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void do_paw_tl1(struct pt_regs *regs);
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void do_vaw(struct pt_regs *regs);
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void do_vaw_tl1(struct pt_regs *regs);
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void do_tof_tl1(struct pt_regs *regs);
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void do_getpsr(struct pt_regs *regs);
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void spitfire_insn_access_exception(struct pt_regs *regs,
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unsigned long sfsr,
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unsigned long sfar);
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void spitfire_insn_access_exception_tl1(struct pt_regs *regs,
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unsigned long sfsr,
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unsigned long sfar);
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void spitfire_data_access_exception(struct pt_regs *regs,
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unsigned long sfsr,
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unsigned long sfar);
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void spitfire_data_access_exception_tl1(struct pt_regs *regs,
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unsigned long sfsr,
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unsigned long sfar);
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void spitfire_access_error(struct pt_regs *regs,
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unsigned long status_encoded,
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unsigned long afar);
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void cheetah_fecc_handler(struct pt_regs *regs,
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unsigned long afsr,
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unsigned long afar);
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void cheetah_cee_handler(struct pt_regs *regs,
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unsigned long afsr,
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unsigned long afar);
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void cheetah_deferred_handler(struct pt_regs *regs,
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unsigned long afsr,
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unsigned long afar);
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void cheetah_plus_parity_error(int type, struct pt_regs *regs);
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void sun4v_insn_access_exception(struct pt_regs *regs,
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unsigned long addr,
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unsigned long type_ctx);
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void sun4v_insn_access_exception_tl1(struct pt_regs *regs,
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unsigned long addr,
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unsigned long type_ctx);
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void sun4v_data_access_exception(struct pt_regs *regs,
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unsigned long addr,
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unsigned long type_ctx);
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void sun4v_data_access_exception_tl1(struct pt_regs *regs,
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unsigned long addr,
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unsigned long type_ctx);
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void sun4v_resum_error(struct pt_regs *regs,
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unsigned long offset);
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void sun4v_resum_overflow(struct pt_regs *regs);
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void sun4v_nonresum_error(struct pt_regs *regs,
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unsigned long offset);
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void sun4v_nonresum_overflow(struct pt_regs *regs);
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extern unsigned long sun4v_err_itlb_vaddr;
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extern unsigned long sun4v_err_itlb_ctx;
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extern unsigned long sun4v_err_itlb_pte;
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extern unsigned long sun4v_err_itlb_error;
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void sun4v_itlb_error_report(struct pt_regs *regs, int tl);
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extern unsigned long sun4v_err_dtlb_vaddr;
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extern unsigned long sun4v_err_dtlb_ctx;
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extern unsigned long sun4v_err_dtlb_pte;
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extern unsigned long sun4v_err_dtlb_error;
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void sun4v_dtlb_error_report(struct pt_regs *regs, int tl);
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void hypervisor_tlbop_error(unsigned long err,
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unsigned long op);
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void hypervisor_tlbop_error_xcall(unsigned long err,
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unsigned long op);
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/* WARNING: The error trap handlers in assembly know the precise
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* layout of the following structure.
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*
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* C-level handlers in traps.c use this information to log the
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* error and then determine how to recover (if possible).
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*/
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struct cheetah_err_info {
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/*0x00*/u64 afsr;
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/*0x08*/u64 afar;
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/* D-cache state */
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/*0x10*/u64 dcache_data[4]; /* The actual data */
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/*0x30*/u64 dcache_index; /* D-cache index */
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/*0x38*/u64 dcache_tag; /* D-cache tag/valid */
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/*0x40*/u64 dcache_utag; /* D-cache microtag */
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/*0x48*/u64 dcache_stag; /* D-cache snooptag */
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/* I-cache state */
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/*0x50*/u64 icache_data[8]; /* The actual insns + predecode */
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/*0x90*/u64 icache_index; /* I-cache index */
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/*0x98*/u64 icache_tag; /* I-cache phys tag */
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/*0xa0*/u64 icache_utag; /* I-cache microtag */
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/*0xa8*/u64 icache_stag; /* I-cache snooptag */
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/*0xb0*/u64 icache_upper; /* I-cache upper-tag */
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/*0xb8*/u64 icache_lower; /* I-cache lower-tag */
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/* E-cache state */
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/*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */
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/*0xe0*/u64 ecache_index; /* E-cache index */
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/*0xe8*/u64 ecache_tag; /* E-cache tag/state */
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/*0xf0*/u64 __pad[32 - 30];
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};
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#define CHAFSR_INVALID ((u64)-1L)
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/* This is allocated at boot time based upon the largest hardware
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* cpu ID in the system. We allocate two entries per cpu, one for
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* TL==0 logging and one for TL >= 1 logging.
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*/
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extern struct cheetah_err_info *cheetah_error_log;
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/* UPA nodes send interrupt packet to UltraSparc with first data reg
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* value low 5 (7 on Starfire) bits holding the IRQ identifier being
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* delivered. We must translate this into a non-vector IRQ so we can
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* set the softint on this cpu.
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*
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* To make processing these packets efficient and race free we use
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* an array of irq buckets below. The interrupt vector handler in
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* entry.S feeds incoming packets into per-cpu pil-indexed lists.
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*
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* If you make changes to ino_bucket, please update hand coded assembler
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* of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
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*/
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struct ino_bucket {
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/*0x00*/unsigned long __irq_chain_pa;
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/* Interrupt number assigned to this INO. */
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/*0x08*/unsigned int __irq;
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/*0x0c*/unsigned int __pad;
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};
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extern struct ino_bucket *ivector_table;
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extern unsigned long ivector_table_pa;
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void init_irqwork_curcpu(void);
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void sun4v_register_mondo_queues(int this_cpu);
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#endif /* CONFIG_SPARC32 */
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#endif /* _ENTRY_H */
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