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d894d964ff
This set of changes displays one major danger of btfixup, interface signatures are not always type checked fully. As seen here the iounit variant of the map_dma_area routine had an incorrect type for one of it's arguments. It turns out to be harmless in this case, but just imagine trying to debug something involving this kind of problem. No thanks. Signed-off-by: David S. Miller <davem@davemloft.net>
144 lines
6.6 KiB
C
144 lines
6.6 KiB
C
#ifndef _ASM_SPARC_DMA_H
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#define _ASM_SPARC_DMA_H
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/* These are irrelevant for Sparc DMA, but we leave it in so that
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* things can compile.
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*/
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#define MAX_DMA_CHANNELS 8
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#define DMA_MODE_READ 1
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#define DMA_MODE_WRITE 2
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#define MAX_DMA_ADDRESS (~0UL)
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/* Useful constants */
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#define SIZE_16MB (16*1024*1024)
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#define SIZE_64K (64*1024)
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/* SBUS DMA controller reg offsets */
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#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
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#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
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#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
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#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
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/* Fields in the cond_reg register */
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/* First, the version identification bits */
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#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
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#define DMA_VERS0 0x00000000 /* Sunray DMA version */
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#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
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#define DMA_VERS1 0x80000000 /* DMA rev 1 */
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#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
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#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
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#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
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#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
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#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
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#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
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#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
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#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
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#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
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#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
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#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
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#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
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#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
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#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
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#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
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#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
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#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
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#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
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#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
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#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
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#define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
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#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
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#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
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#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
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#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
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#define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
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#define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
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#define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
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#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
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#define DMA_BRST64 0x000c0000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
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#define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
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#define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
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#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
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#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
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#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
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#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
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#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
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#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
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#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
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#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
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#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
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#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
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#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
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#define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
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/* Values describing the burst-size property from the PROM */
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#define DMA_BURST1 0x01
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#define DMA_BURST2 0x02
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#define DMA_BURST4 0x04
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#define DMA_BURST8 0x08
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#define DMA_BURST16 0x10
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#define DMA_BURST32 0x20
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#define DMA_BURST64 0x40
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#define DMA_BURSTBITS 0x7f
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/* From PCI */
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#ifdef CONFIG_PCI
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extern int isa_dma_bridge_buggy;
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#else
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#define isa_dma_bridge_buggy (0)
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#endif
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#ifdef CONFIG_SPARC32
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/* Routines for data transfer buffers. */
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struct device;
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struct scatterlist;
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struct sparc32_dma_ops {
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__u32 (*get_scsi_one)(struct device *, char *, unsigned long);
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void (*get_scsi_sgl)(struct device *, struct scatterlist *, int);
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void (*release_scsi_one)(struct device *, __u32, unsigned long);
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void (*release_scsi_sgl)(struct device *, struct scatterlist *,int);
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#ifdef CONFIG_SBUS
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int (*map_dma_area)(struct device *, dma_addr_t *, unsigned long, unsigned long, int);
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void (*unmap_dma_area)(struct device *, unsigned long, int);
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#endif
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};
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extern const struct sparc32_dma_ops *sparc32_dma_ops;
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#define mmu_get_scsi_one(dev,vaddr,len) \
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sparc32_dma_ops->get_scsi_one(dev, vaddr, len)
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#define mmu_get_scsi_sgl(dev,sg,sz) \
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sparc32_dma_ops->get_scsi_sgl(dev, sg, sz)
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#define mmu_release_scsi_one(dev,vaddr,len) \
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sparc32_dma_ops->release_scsi_one(dev, vaddr,len)
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#define mmu_release_scsi_sgl(dev,sg,sz) \
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sparc32_dma_ops->release_scsi_sgl(dev, sg, sz)
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#ifdef CONFIG_SBUS
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/*
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* mmu_map/unmap are provided by iommu/iounit; Invalid to call on IIep.
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*
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* The mmu_map_dma_area establishes two mappings in one go.
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* These mappings point to pages normally mapped at 'va' (linear address).
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* First mapping is for CPU visible address at 'a', uncached.
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* This is an alias, but it works because it is an uncached mapping.
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* Second mapping is for device visible address, or "bus" address.
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* The bus address is returned at '*pba'.
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*
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* These functions seem distinct, but are hard to split.
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* On sun4m, page attributes depend on the CPU type, so we have to
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* know if we are mapping RAM or I/O, so it has to be an additional argument
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* to a separate mapping function for CPU visible mappings.
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*/
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#define sbus_map_dma_area(dev,pba,va,a,len) \
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sparc32_dma_ops->map_dma_area(dev, pba, va, a, len)
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#define sbus_unmap_dma_area(dev,ba,len) \
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sparc32_dma_ops->unmap_dma_area(dev, ba, len)
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#endif /* CONFIG_SBUS */
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#endif
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#endif /* !(_ASM_SPARC_DMA_H) */
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