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Add support for the Everest-semi ES8311 codec. Everest-semi ES8311 codec is a low-power mono audio codec with I2S audio interface and I2C control. Supported features: * Both master and slave mode. Master clock is optional in slave mode. * Sample rates from 8KHz to 96KHz. * Sample formats: S16_LE, S18_3LE, S20_3LE, S24_3LE, S24_LE and S32_LE. * I2S formats: I2S, LEFT_J, DSP_A, DSP_B. * BCLK and FSYNC clocks inversion. * Component suspend/resume. * ADC, PGA, DAC controls. * ADC DSP controls: volume, fade (ramp rate), ALC, automute, HPF, EQ. * DAC DSP controls: volume, fade (ramp rate), DRC, EQ. * DAPM routes: capture path with input source selection (differential MIC/DMIC) and AIF channel source selection; playback path with DAC channel source selection. Limitations: * Support only for master clocks with a ratio of ADC (or DAC) clock to LRCLK equal to 256. This to keep the default ADC and DAC oversampling and ADC scale settings. Anyway all 8-96KHz sample rates are supported when the ratio of MCLK to sample rate is 32, 64, 128, 256, 384 or 512 (upper limit due to max MCLK freq of 49.2MHz). * Coefficients for ADC HPF and ADC/DAC EQ not supported. * Digital mic supported but not tested. * S18_3LE, S20_3LE and S24_3LE formats supported but not tested. Signed-off-by: Matteo Martelli <matteomartelli3@gmail.com> Link: https://msgid.link/r/20240522164722.954656-3-matteomartelli3@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
163 lines
5.0 KiB
C
163 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* es8311.c -- es8311 ALSA SoC audio driver
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*
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* Copyright (C) 2024 Matteo Martelli <matteomartelli3@gmail.com>
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*
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* Author: Matteo Martelli <matteomartelli3@gmail.com>
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*/
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#ifndef _ES8311_H
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#define _ES8311_H
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#include <linux/bitops.h>
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#define ES8311_RESET 0x00
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#define ES8311_RESET_CSM_ON BIT(7)
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#define ES8311_RESET_MSC BIT(6)
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#define ES8311_RESET_RST_MASK GENMASK(4, 0)
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/* Clock Manager Registers */
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#define ES8311_CLKMGR1 0x01
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#define ES8311_CLKMGR1_MCLK_SEL BIT(7)
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#define ES8311_CLKMGR1_MCLK_ON BIT(5)
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#define ES8311_CLKMGR1_BCLK_ON BIT(4)
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#define ES8311_CLKMGR1_CLKADC_ON_SHIFT 3
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#define ES8311_CLKMGR1_CLKDAC_ON_SHIFT 2
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#define ES8311_CLKMGR1_ANACLKADC_ON_SHIFT 1
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#define ES8311_CLKMGR1_ANACLKDAC_ON_SHIFT 0
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#define ES8311_CLKMGR2 0x02
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#define ES8311_CLKMGR2_DIV_PRE_MASK GENMASK(7, 5)
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#define ES8311_CLKMGR2_DIV_PRE_SHIFT 5
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#define ES8311_CLKMGR2_DIV_PRE_MAX 0x07
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#define ES8311_CLKMGR2_MULT_PRE_MASK GENMASK(4, 3)
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#define ES8311_CLKMGR2_MULT_PRE_SHIFT 3
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#define ES8311_CLKMGR3 0x03
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#define ES8311_CLKMGR4 0x04
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#define ES8311_CLKMGR5 0x05
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#define ES8311_CLKMGR5_ADC_DIV_MASK GENMASK(7, 4)
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#define ES8311_CLKMGR5_ADC_DIV_SHIFT 4
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#define ES8311_CLKMGR5_DAC_DIV_MASK GENMASK(3, 0)
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#define ES8311_CLKMGR5_DAC_DIV_SHIFT 0
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#define ES8311_CLKMGR6 0x06
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#define ES8311_CLKMGR6_BCLK_INV BIT(5)
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#define ES8311_CLKMGR6_DIV_BCLK_MASK GENMASK(4, 0)
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#define ES8311_CLKMGR7 0x07
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#define ES8311_CLKMGR7_LRCLK_DIV_H_MASK GENMASK(3, 0)
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#define ES8311_CLKMGR8 0x08
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#define ES8311_CLKMGR_LRCLK_DIV_MAX 0x0FFF
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/* SDP Mode Registers */
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#define ES8311_SDP_IN 0x09
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#define ES8311_SDP_IN_SEL_SHIFT 7
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#define ES8311_SDP_OUT 0x0A
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/* Following values are the same for both SPD_IN and SDP_OUT */
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#define ES8311_SDP_MUTE_SHIFT 6
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#define ES8311_SDP_LRP BIT(5)
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#define ES8311_SDP_WL_MASK GENMASK(4, 2)
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#define ES8311_SDP_WL_SHIFT 2
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#define ES8311_SDP_WL_24 0x00
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#define ES8311_SDP_WL_20 0x01
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#define ES8311_SDP_WL_18 0x02
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#define ES8311_SDP_WL_16 0x03
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#define ES8311_SDP_WL_32 0x04
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#define ES8311_SDP_FMT_MASK GENMASK(1, 0)
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#define ES8311_SDP_FMT_I2S 0x00
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#define ES8311_SDP_FMT_LEFT_J 0x01
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#define ES8311_SDP_FMT_DSP 0x03
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/* System registers */
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#define ES8311_SYS1 0x0B
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#define ES8311_SYS2 0x0C
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#define ES8311_SYS3 0x0D
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#define ES8311_SYS3_PDN_ANA_SHIFT 7
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#define ES8311_SYS3_PDN_IBIASGEN_SHIFT 6
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#define ES8311_SYS3_PDN_ADCBIASGEN_SHIFT 5
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#define ES8311_SYS3_PDN_ADCVREFGEN_SHIFT 4
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#define ES8311_SYS3_PDN_DACVREFGEN_SHIFT 3
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#define ES8311_SYS3_PDN_VREF_SHIFT 2
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#define ES8311_SYS3_PDN_VMIDSEL_MASK GENMASK(1, 0)
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#define ES8311_SYS3_PDN_VMIDSEL_POWER_DOWN 0
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#define ES8311_SYS3_PDN_VMIDSEL_STARTUP_NORMAL_SPEED 1
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#define ES8311_SYS3_PDN_VMIDSEL_NORMAL_OPERATION 2
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#define ES8311_SYS3_PDN_VMIDSEL_STARTUP_FAST_SPEED 3
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#define ES8311_SYS4 0x0E
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#define ES8311_SYS4_PDN_PGA_SHIFT 6
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#define ES8311_SYS4_PDN_MOD_SHIFT 5
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#define ES8311_SYS5 0x0F
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#define ES8311_SYS6 0x10
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#define ES8311_SYS7 0x11
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#define ES8311_SYS8 0x12
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#define ES8311_SYS8_PDN_DAC_SHIFT 1
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#define ES8311_SYS9 0x13
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#define ES8311_SYS9_HPSW_SHIFT 4
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#define ES8311_SYS10 0x14
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#define ES8311_SYS10_DMIC_ON_SHIFT 6
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#define ES8311_SYS10_LINESEL_SHIFT 4
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#define ES8311_SYS10_PGAGAIN_SHIFT 0
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#define ES8311_SYS10_PGAGAIN_MAX 0x0A
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/* ADC Registers*/
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#define ES8311_ADC1 0x15
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#define ES8311_ADC1_RAMPRATE_SHIFT 4
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#define ES8311_ADC2 0x16
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#define ES8311_ADC2_INV_SHIFT 4
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#define ES8311_ADC2_SCALE_SHIFT 0
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#define ES8311_ADC2_SCALE_MAX 0x07
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#define ES8311_ADC3 0x17
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#define ES8311_ADC3_VOLUME_SHIFT 0
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#define ES8311_ADC3_VOLUME_MAX 0xFF
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#define ES8311_ADC4 0x18
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#define ES8311_ADC4_ALC_EN_SHIFT 7
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#define ES8311_ADC4_AUTOMUTE_EN_SHIFT 6
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#define ES8311_ADC4_ALC_WINSIZE_SHIFT 0
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#define ES8311_ADC5 0x19
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#define ES8311_ADC5_ALC_MAXLEVEL_SHIFT 4
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#define ES8311_ADC5_ALC_MAXLEVEL_MAX 0x0F
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#define ES8311_ADC5_ALC_MINLEVEL_SHIFT 0
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#define ES8311_ADC5_ALC_MINLEVEL_MAX 0x0F
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#define ES8311_ADC6 0x1A
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#define ES8311_ADC6_AUTOMUTE_WS_SHIFT 4
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#define ES8311_ADC6_AUTOMUTE_NG_SHIFT 0
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#define ES8311_ADC6_AUTOMUTE_NG_MAX 0x0F
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#define ES8311_ADC7 0x1B
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#define ES8311_ADC7_AUTOMUTE_VOL_SHIFT 5
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#define ES8311_ADC7_AUTOMUTE_VOL_MAX 0x07
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#define ES8311_ADC8 0x1C
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#define ES8311_ADC8_EQBYPASS_SHIFT 6
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#define ES8311_ADC8_HPF_SHIFT 5
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/* DAC Registers */
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#define ES8311_DAC1 0x31
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#define ES8311_DAC1_DAC_DSMMUTE BIT(6)
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#define ES8311_DAC1_DAC_DEMMUTE BIT(5)
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#define ES8311_DAC2 0x32
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#define ES8311_DAC2_VOLUME_MAX 0xFF
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#define ES8311_DAC3 0x33
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#define ES8311_DAC4 0x34
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#define ES8311_DAC4_DRC_EN_SHIFT 7
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#define ES8311_DAC4_DRC_WINSIZE_SHIFT 0
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#define ES8311_DAC5 0x35
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#define ES8311_DAC5_DRC_MAXLEVEL_SHIFT 4
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#define ES8311_DAC5_DRC_MAXLEVEL_MAX 0x0F
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#define ES8311_DAC5_DRC_MINLEVEL_SHIFT 0
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#define ES8311_DAC5_DRC_MINLEVEL_MAX 0x0F
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#define ES8311_DAC6 0x37
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#define ES8311_DAC6_RAMPRATE_SHIFT 4
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#define ES8311_DAC6_EQBYPASS_SHIFT 3
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/* GPIO Registers */
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#define ES8311_GPIO 0x44
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#define ES8311_GPIO_ADC2DAC_SEL_SHIFT 7
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#define ES8311_GPIO_ADCDAT_SEL_SHIFT 4
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/* Chip Info Registers */
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#define ES8311_CHIPID1 0xFD /* 0x83 */
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#define ES8311_CHIPID2 0xFE /* 0x11 */
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#define ES8311_CHIPVER 0xFF
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#define ES8311_REG_MAX 0xFF
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#endif
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