mirror of
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3f386cb8ee
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Merge tag 'pci-v6.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull pci updates from Bjorn Helgaas:
"Enumeration:
- Define PCIE_RESET_CONFIG_DEVICE_WAIT_MS for the generic 100ms
required after reset before config access (Kevin Xie)
- Define PCIE_T_RRS_READY_MS for the generic 100ms required after
reset before config access (probably should be unified with
PCIE_RESET_CONFIG_DEVICE_WAIT_MS) (Damien Le Moal)
Resource management:
- Rename find_resource() to find_resource_space() to be more
descriptive (Ilpo Järvinen)
- Export find_resource_space() for use by PCI core, which needs to
learn whether there is available space for a bridge window (Ilpo
Järvinen)
- Prevent double counting of resources so window size doesn't grow on
each remove/rescan cycle (Ilpo Järvinen)
- Relax bridge window sizing algorithm so a device doesn't break
simply because it was removed and rescanned (Ilpo Järvinen)
- Evaluate the ACPI PRESERVE_BOOT_CONFIG _DSM in
pci_register_host_bridge() (not acpi_pci_root_create()) so we can
unify it with similar DT functionality (Vidya Sagar)
- Extend use of DT "linux,pci-probe-only" property so it works
per-host bridge as well as globally (Vidya Sagar)
- Unify support for ACPI PRESERVE_BOOT_CONFIG _DSM and the DT
"linux,pci-probe-only" property in pci_preserve_config() (Vidya
Sagar)
Driver binding:
- Add devres infrastructure for managed request and map of partial
BAR resources (Philipp Stanner)
- Deprecate pcim_iomap_table() because uses like
"pcim_iomap_table()[0]" have no good way to return errors (Philipp
Stanner)
- Add an always-managed pcim_request_region() for use instead of
pci_request_region() and similar, which are sometimes managed
depending on whether pcim_enable_device() has been called
previously (Philipp Stanner)
- Reimplement pcim_set_mwi() so it doesn't need to keep store MWI
state (Philipp Stanner)
- Add pcim_intx() for use instead of pci_intx(), which is sometimes
managed depending on whether pcim_enable_device() has been called
previously (Philipp Stanner)
- Add managed pcim_iomap_range() to allow mapping of a partial BAR
(Philipp Stanner)
- Fix a devres mapping leak in drm/vboxvideo (Philipp Stanner)
Error handling:
- Add missing bridge locking in device reset path and add a warning
for other possible lock issues (Dan Williams)
- Fix use-after-free on concurrent DPC and hot-removal (Lukas Wunner)
Power management:
- Disable AER and DPC during suspend to avoid spurious wakeups if
they share an interrupt with PME (Kai-Heng Feng)
PCIe native device hotplug:
- Detect if a device was removed or replaced during system sleep so
we don't assume a new device is the one that used to be there
(Lukas Wunner)
Virtualization:
- Add an ACS quirk for Broadcom BCM5760X multi-function NIC; it
prevents transactions between functions even though it doesn't
advertise ACS, so the functions can be attached individually via
VFIO (Ajit Khaparde)
Peer-to-peer DMA:
- Add a "pci=config_acs=" kernel command-line parameter to relax
default ACS settings to enable additional peer-to-peer
configurations. Requires expert knowledge of topology and ACS
operation (Vidya Sagar)
Endpoint framework:
- Remove unused struct pci_epf_group.type_group (Christophe JAILLET)
- Fix error handling in vpci_scan_bus() and epf_ntb_epc_cleanup()
(Dan Carpenter)
- Make struct pci_epc_class constant (Greg Kroah-Hartman)
- Remove unused pci_endpoint_test_bar_{readl,writel} functions
(Jiapeng Chong)
- Rename "BME" to "Bus Master Enable" (Manivannan Sadhasivam)
- Rename struct pci_epc_event_ops.core_init() callback to epc_init()
(Manivannan Sadhasivam)
- Move DMA init to MHI .epc_init() callback for uniformity
(Manivannan Sadhasivam)
- Cancel EPF test delayed work when link goes down (Manivannan
Sadhasivam)
- Add struct pci_epc_event_ops.epc_deinit() callback for cleanup
needed on fundamental reset (Manivannan Sadhasivam)
- Add 64KB alignment to endpoint test to support Rockchip rk3588
(Niklas Cassel)
- Optimize endpoint test by using memcpy() instead of readl() (Niklas
Cassel)
Device tree bindings:
- Add generic "ats-supported" property to advertise that a PCIe Root
Complex supports ATS (Jean-Philippe Brucker)
Amazon Annapurna Labs PCIe controller driver:
- Validate IORESOURCE_BUS presence to avoid NULL pointer dereference
(Aleksandr Mishin)
Axis ARTPEC-6 PCIe controller driver:
- Rename .cpu_addr_fixup() parameter to reflect that it is a PCI
address, not a CPU address (Niklas Cassel)
Freescale i.MX6 PCIe controller driver:
- Convert to agnostic GPIO API (Andy Shevchenko)
Freescale Layerscape PCIe controller driver:
- Make struct mobiveil_rp_ops constant (Christophe JAILLET)
- Use new generic dw_pcie_ep_linkdown() to handle link-down events
(Manivannan Sadhasivam)
HiSilicon Kirin PCIe controller driver:
- Convert to agnostic GPIO API (Andy Shevchenko)
- Use _scoped() iterator for OF children to ensure refcounts are
decremented at loop exit (Javier Carrasco)
Intel VMD host bridge driver:
- Create sysfs "domain" symlink before downstream devices are exposed
to userspace by pci_bus_add_devices() (Jiwei Sun)
Loongson PCIe controller driver:
- Enable MSI when LS7A is used with new CPUs that have integrated
PCIe Root Complex, e.g., Loongson-3C6000, so downstream devices can
use MSI (Huacai Chen)
Microchip AXI PolarFlare PCIe controller driver:
- Move pcie-microchip-host.c to a new PLDA directory (Minda Chen)
- Factor PLDA generic items out to a common
plda,xpressrich3-axi-common.yaml binding (Minda Chen)
- Factor PLDA generic data structures and code out to shared
pcie-plda.h, pcie-plda-host.c (Minda Chen)
- Add PLDA generic interrupt handling with a .request_event_irq()
callback for vendor-specific events (Minda Chen)
- Add PLDA generic host init/deinit and map bus functions for use by
vendor-specific drivers (Minda Chen)
- Rework to use PLDA core (Minda Chen)
Microsoft Hyper-V host bridge driver:
- Return zero, not garbage, when reading PCI_INTERRUPT_PIN (Wei Liu)
NVIDIA Tegra194 PCIe controller driver:
- Remove unused struct tegra_pcie_soc (Dr. David Alan Gilbert)
- Set 64KB inbound ATU alignment restriction (Jon Hunter)
Qualcomm PCIe controller driver:
- Make the MHI reg region mandatory for X1E80100, since all PCIe
controllers have it (Abel Vesa)
- Prevent use of uninitialized data and possible error pointer
dereference (Dan Carpenter)
- Return error, not success, if dev_pm_opp_find_freq_floor() fails
(Dan Carpenter)
- Add Operating Performance Points (OPP) support to scale performance
state based on aggregate link bandwidth to improve SoC power
efficiency (Krishna chaitanya chundru)
- Vote for the CPU-PCIe ICC (interconnect) path to ensure it stays
active even if other drivers don't vote for it (Krishna chaitanya
chundru)
- Use devm_clk_bulk_get_all() to get all the clocks from DT to avoid
writing out all the clock names (Manivannan Sadhasivam)
- Add DT binding and driver support for the SA8775P SoC (Mrinmay
Sarkar)
- Add HDMA support for the SA8775P SoC (Mrinmay Sarkar)
- Override the SA8775P NO_SNOOP default to avoid possible memory
corruption (Mrinmay Sarkar)
- Make sure resources are disabled during PERST# assertion, even if
the link is already disabled (Manivannan Sadhasivam)
- Use new generic dw_pcie_ep_linkdown() to handle link-down events
(Manivannan Sadhasivam)
- Add DT and endpoint driver support for the SA8775P SoC (Mrinmay
Sarkar)
- Add Hyper DMA (HDMA) support for the SA8775P SoC and enable it in
the EPF MHI driver (Mrinmay Sarkar)
- Set PCIE_PARF_NO_SNOOP_OVERIDE to override the default NO_SNOOP
attribute on the SA8775P SoC (both Root Complex and Endpoint mode)
to avoid possible memory corruption (Mrinmay Sarkar)
Renesas R-Car PCIe controller driver:
- Demote WARN() to dev_warn_ratelimited() in rcar_pcie_wakeup() to
avoid unnecessary backtrace (Marek Vasut)
- Add DT and driver support for R-Car V4H (R8A779G0) host and
endpoint. This requires separate proprietary firmware (Yoshihiro
Shimoda)
Rockchip PCIe controller driver:
- Assert PERST# for 100ms after power is stable (Damien Le Moal)
- Wait PCIE_T_RRS_READY_MS (100ms) after reset before starting
configuration (Damien Le Moal)
- Use GPIOD_OUT_LOW flag while requesting ep_gpio to fix a firmware
crash on Qcom-based modems with Rockpro64 board (Manivannan
Sadhasivam)
Rockchip DesignWare PCIe controller driver:
- Factor common parts of rockchip-dw-pcie DT binding to be shared by
Root Complex and Endpoint mode (Niklas Cassel)
- Add missing INTx signals to common DT binding (Niklas Cassel)
- Add eDMA items to DT binding for Endpoint controller (Niklas
Cassel)
- Fix initial dw-rockchip PERST# GPIO value to prevent unnecessary
short assert/deassert that causes issues with some WLAN controllers
(Niklas Cassel)
- Refactor dw-rockchip and add support for Endpoint mode (Niklas
Cassel)
- Call pci_epc_init_notify() and drop dw_pcie_ep_init_notify()
wrapper (Niklas Cassel)
- Add error messages in .probe() error paths to improve user
experience (Uwe Kleine-König)
Samsung Exynos PCIe controller driver:
- Use bulk clock APIs to simplify clock setup (Shradha Todi)
StarFive PCIe controller driver:
- Add DT binding and driver support for the StarFive JH7110
PLDA-based PCIe controller (Minda Chen)
Synopsys DesignWare PCIe controller driver:
- Add generic support for sending PME_Turn_Off when system suspends
(Frank Li)
- Fix incorrect interpretation of iATU slot 0 after PERST#
assert/deassert (Frank Li)
- Use msleep() instead of usleep_range() while waiting for link
(Konrad Dybcio)
- Refactor dw_pcie_edma_find_chip() to enable adding support for
Hyper DMA (HDMA) (Manivannan Sadhasivam)
- Enable drivers to supply the eDMA channel count since some can't
auto detect this (Manivannan Sadhasivam)
- Call pci_epc_init_notify() and drop dw_pcie_ep_init_notify()
wrapper (Manivannan Sadhasivam)
- Pass the eDMA mapping format directly from drivers instead of
maintaining a capability for it (Manivannan Sadhasivam)
- Add generic dw_pcie_ep_linkdown() to notify EPF drivers about
link-down events and restore non-sticky DWC registers lost on link
down (Manivannan Sadhasivam)
- Add vendor-specific "apb" reg name, interrupt names, INTx names to
generic binding (Niklas Cassel)
- Enforce DWC restriction that 64-bit BARs must start with an
even-numbered BAR (Niklas Cassel)
- Consolidate args of dw_pcie_prog_outbound_atu() into a structure
(Yoshihiro Shimoda)
- Add support for endpoints to send Message TLPs, e.g., for INTx
emulation (Yoshihiro Shimoda)
TI DRA7xx PCIe controller driver:
- Rename .cpu_addr_fixup() parameter to reflect that it is a PCI
address, not a CPU address (Niklas Cassel)
TI Keystone PCIe controller driver:
- Validate IORESOURCE_BUS presence to avoid NULL pointer dereference
(Aleksandr Mishin)
- Work around AM65x/DRA80xM Errata #i2037 that corrupts TLPs and
causes processor hangs by limiting Max_Read_Request_Size (MRRS) and
Max_Payload_Size (MPS) (Kishon Vijay Abraham I)
- Leave BAR 0 disabled for AM654x to fix a regression caused by
6ab15b5e70
("PCI: dwc: keystone: Convert .scan_bus() callback to
use add_bus"), which caused a 45-second boot delay (Siddharth
Vadapalli)
Xilinx Versal CPM PCIe controller driver:
- Fix overlapping bridge registers and 32-bit BAR addresses in DT
binding (Thippeswamy Havalige)
MicroSemi Switchtec management driver:
- Make struct switchtec_class constant (Greg Kroah-Hartman)
Miscellaneous:
- Remove unused struct acpi_handle_node (Dr. David Alan Gilbert)
- Add missing MODULE_DESCRIPTION() macros (Jeff Johnson)"
* tag 'pci-v6.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (154 commits)
PCI: loongson: Enable MSI in LS7A Root Complex
PCI: Extend ACS configurability
PCI: Add missing bridge lock to pci_bus_lock()
drm/vboxvideo: fix mapping leaks
PCI: Add managed pcim_iomap_range()
PCI: Remove legacy pcim_release()
PCI: Add managed pcim_intx()
PCI: vmd: Create domain symlink before pci_bus_add_devices()
PCI: qcom: Prevent use of uninitialized data in qcom_pcie_suspend_noirq()
PCI: qcom: Prevent potential error pointer dereference
PCI: qcom: Fix missing error code in qcom_pcie_probe()
PCI: Give pcim_set_mwi() its own devres cleanup callback
PCI: Move struct pci_devres.pinned bit to struct pci_dev
PCI: Remove struct pci_devres.enabled status bit
PCI: Document hybrid devres hazards
PCI: Add managed pcim_request_region()
PCI: Deprecate pcim_iomap_table(), pcim_iomap_regions_request_all()
PCI: Add managed partial-BAR request and map infrastructure
PCI: Add devres helpers for iomap table
PCI: Add and use devres helper for bit masks
...
829 lines
22 KiB
C
829 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* PCI <-> OF mapping helpers
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*
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* Copyright 2011 IBM Corp.
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*/
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#define pr_fmt(fmt) "PCI: OF: " fmt
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#include <linux/cleanup.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/platform_device.h>
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#include "pci.h"
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#ifdef CONFIG_PCI
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/**
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* pci_set_of_node - Find and set device's DT device_node
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* @dev: the PCI device structure to fill
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*
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* Returns 0 on success with of_node set or when no device is described in the
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* DT. Returns -ENODEV if the device is present, but disabled in the DT.
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*/
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int pci_set_of_node(struct pci_dev *dev)
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{
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if (!dev->bus->dev.of_node)
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return 0;
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struct device_node *node __free(device_node) =
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of_pci_find_child_device(dev->bus->dev.of_node, dev->devfn);
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if (!node)
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return 0;
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struct device *pdev __free(put_device) =
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bus_find_device_by_of_node(&platform_bus_type, node);
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if (pdev)
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dev->bus->dev.of_node_reused = true;
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device_set_node(&dev->dev, of_fwnode_handle(no_free_ptr(node)));
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return 0;
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}
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void pci_release_of_node(struct pci_dev *dev)
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{
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of_node_put(dev->dev.of_node);
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device_set_node(&dev->dev, NULL);
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}
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void pci_set_bus_of_node(struct pci_bus *bus)
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{
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struct device_node *node;
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if (bus->self == NULL) {
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node = pcibios_get_phb_of_node(bus);
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} else {
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node = of_node_get(bus->self->dev.of_node);
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if (node && of_property_read_bool(node, "external-facing"))
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bus->self->external_facing = true;
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}
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device_set_node(&bus->dev, of_fwnode_handle(node));
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}
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void pci_release_bus_of_node(struct pci_bus *bus)
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{
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of_node_put(bus->dev.of_node);
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device_set_node(&bus->dev, NULL);
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}
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struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus)
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{
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/* This should only be called for PHBs */
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if (WARN_ON(bus->self || bus->parent))
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return NULL;
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/*
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* Look for a node pointer in either the intermediary device we
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* create above the root bus or its own parent. Normally only
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* the later is populated.
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*/
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if (bus->bridge->of_node)
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return of_node_get(bus->bridge->of_node);
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if (bus->bridge->parent && bus->bridge->parent->of_node)
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return of_node_get(bus->bridge->parent->of_node);
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return NULL;
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}
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struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus)
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{
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#ifdef CONFIG_IRQ_DOMAIN
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struct irq_domain *d;
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if (!bus->dev.of_node)
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return NULL;
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/* Start looking for a phandle to an MSI controller. */
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d = of_msi_get_domain(&bus->dev, bus->dev.of_node, DOMAIN_BUS_PCI_MSI);
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if (d)
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return d;
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/*
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* If we don't have an msi-parent property, look for a domain
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* directly attached to the host bridge.
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*/
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d = irq_find_matching_host(bus->dev.of_node, DOMAIN_BUS_PCI_MSI);
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if (d)
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return d;
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return irq_find_host(bus->dev.of_node);
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#else
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return NULL;
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#endif
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}
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bool pci_host_of_has_msi_map(struct device *dev)
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{
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if (dev && dev->of_node)
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return of_get_property(dev->of_node, "msi-map", NULL);
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return false;
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}
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static inline int __of_pci_pci_compare(struct device_node *node,
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unsigned int data)
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{
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int devfn;
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devfn = of_pci_get_devfn(node);
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if (devfn < 0)
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return 0;
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return devfn == data;
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}
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struct device_node *of_pci_find_child_device(struct device_node *parent,
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unsigned int devfn)
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{
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struct device_node *node, *node2;
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for_each_child_of_node(parent, node) {
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if (__of_pci_pci_compare(node, devfn))
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return node;
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/*
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* Some OFs create a parent node "multifunc-device" as
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* a fake root for all functions of a multi-function
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* device we go down them as well.
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*/
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if (of_node_name_eq(node, "multifunc-device")) {
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for_each_child_of_node(node, node2) {
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if (__of_pci_pci_compare(node2, devfn)) {
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of_node_put(node);
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return node2;
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}
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}
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}
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}
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return NULL;
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}
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EXPORT_SYMBOL_GPL(of_pci_find_child_device);
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/**
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* of_pci_get_devfn() - Get device and function numbers for a device node
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* @np: device node
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*
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* Parses a standard 5-cell PCI resource and returns an 8-bit value that can
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* be passed to the PCI_SLOT() and PCI_FUNC() macros to extract the device
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* and function numbers respectively. On error a negative error code is
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* returned.
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*/
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int of_pci_get_devfn(struct device_node *np)
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{
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u32 reg[5];
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int error;
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error = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg));
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if (error)
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return error;
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return (reg[0] >> 8) & 0xff;
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}
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EXPORT_SYMBOL_GPL(of_pci_get_devfn);
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/**
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* of_pci_parse_bus_range() - parse the bus-range property of a PCI device
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* @node: device node
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* @res: address to a struct resource to return the bus-range
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*
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* Returns 0 on success or a negative error-code on failure.
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*/
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int of_pci_parse_bus_range(struct device_node *node, struct resource *res)
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{
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u32 bus_range[2];
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int error;
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error = of_property_read_u32_array(node, "bus-range", bus_range,
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ARRAY_SIZE(bus_range));
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if (error)
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return error;
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res->name = node->name;
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res->start = bus_range[0];
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res->end = bus_range[1];
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res->flags = IORESOURCE_BUS;
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return 0;
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}
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EXPORT_SYMBOL_GPL(of_pci_parse_bus_range);
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/**
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* of_get_pci_domain_nr - Find the host bridge domain number
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* of the given device node.
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* @node: Device tree node with the domain information.
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*
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* This function will try to obtain the host bridge domain number by finding
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* a property called "linux,pci-domain" of the given device node.
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*
|
|
* Return:
|
|
* * > 0 - On success, an associated domain number.
|
|
* * -EINVAL - The property "linux,pci-domain" does not exist.
|
|
* * -ENODATA - The linux,pci-domain" property does not have value.
|
|
* * -EOVERFLOW - Invalid "linux,pci-domain" property value.
|
|
*
|
|
* Returns the associated domain number from DT in the range [0-0xffff], or
|
|
* a negative value if the required property is not found.
|
|
*/
|
|
int of_get_pci_domain_nr(struct device_node *node)
|
|
{
|
|
u32 domain;
|
|
int error;
|
|
|
|
error = of_property_read_u32(node, "linux,pci-domain", &domain);
|
|
if (error)
|
|
return error;
|
|
|
|
return (u16)domain;
|
|
}
|
|
EXPORT_SYMBOL_GPL(of_get_pci_domain_nr);
|
|
|
|
/**
|
|
* of_pci_preserve_config - Return true if the boot configuration needs to
|
|
* be preserved
|
|
* @node: Device tree node.
|
|
*
|
|
* Look for "linux,pci-probe-only" property for a given PCI controller's
|
|
* node and return true if found. Also look in the chosen node if the
|
|
* property is not found in the given controller's node. Having this
|
|
* property ensures that the kernel doesn't reconfigure the BARs and bridge
|
|
* windows that are already done by the platform firmware.
|
|
*
|
|
* Return: true if the property exists; false otherwise.
|
|
*/
|
|
bool of_pci_preserve_config(struct device_node *node)
|
|
{
|
|
u32 val = 0;
|
|
int ret;
|
|
|
|
if (!node) {
|
|
pr_warn("device node is NULL, trying with of_chosen\n");
|
|
node = of_chosen;
|
|
}
|
|
|
|
retry:
|
|
ret = of_property_read_u32(node, "linux,pci-probe-only", &val);
|
|
if (ret) {
|
|
if (ret == -ENODATA || ret == -EOVERFLOW) {
|
|
pr_warn("Incorrect value for linux,pci-probe-only in %pOF, ignoring\n",
|
|
node);
|
|
return false;
|
|
}
|
|
if (ret == -EINVAL) {
|
|
if (node == of_chosen)
|
|
return false;
|
|
|
|
node = of_chosen;
|
|
goto retry;
|
|
}
|
|
}
|
|
|
|
if (val)
|
|
return true;
|
|
else
|
|
return false;
|
|
}
|
|
|
|
/**
|
|
* of_pci_check_probe_only - Setup probe only mode if linux,pci-probe-only
|
|
* is present and valid
|
|
*/
|
|
void of_pci_check_probe_only(void)
|
|
{
|
|
if (of_pci_preserve_config(of_chosen))
|
|
pci_add_flags(PCI_PROBE_ONLY);
|
|
else
|
|
pci_clear_flags(PCI_PROBE_ONLY);
|
|
}
|
|
EXPORT_SYMBOL_GPL(of_pci_check_probe_only);
|
|
|
|
/**
|
|
* devm_of_pci_get_host_bridge_resources() - Resource-managed parsing of PCI
|
|
* host bridge resources from DT
|
|
* @dev: host bridge device
|
|
* @busno: bus number associated with the bridge root bus
|
|
* @bus_max: maximum number of buses for this bridge
|
|
* @resources: list where the range of resources will be added after DT parsing
|
|
* @ib_resources: list where the range of inbound resources (with addresses
|
|
* from 'dma-ranges') will be added after DT parsing
|
|
* @io_base: pointer to a variable that will contain on return the physical
|
|
* address for the start of the I/O range. Can be NULL if the caller doesn't
|
|
* expect I/O ranges to be present in the device tree.
|
|
*
|
|
* This function will parse the "ranges" property of a PCI host bridge device
|
|
* node and setup the resource mapping based on its content. It is expected
|
|
* that the property conforms with the Power ePAPR document.
|
|
*
|
|
* It returns zero if the range parsing has been successful or a standard error
|
|
* value if it failed.
|
|
*/
|
|
static int devm_of_pci_get_host_bridge_resources(struct device *dev,
|
|
unsigned char busno, unsigned char bus_max,
|
|
struct list_head *resources,
|
|
struct list_head *ib_resources,
|
|
resource_size_t *io_base)
|
|
{
|
|
struct device_node *dev_node = dev->of_node;
|
|
struct resource *res, tmp_res;
|
|
struct resource *bus_range;
|
|
struct of_pci_range range;
|
|
struct of_pci_range_parser parser;
|
|
const char *range_type;
|
|
int err;
|
|
|
|
if (io_base)
|
|
*io_base = (resource_size_t)OF_BAD_ADDR;
|
|
|
|
bus_range = devm_kzalloc(dev, sizeof(*bus_range), GFP_KERNEL);
|
|
if (!bus_range)
|
|
return -ENOMEM;
|
|
|
|
dev_info(dev, "host bridge %pOF ranges:\n", dev_node);
|
|
|
|
err = of_pci_parse_bus_range(dev_node, bus_range);
|
|
if (err) {
|
|
bus_range->start = busno;
|
|
bus_range->end = bus_max;
|
|
bus_range->flags = IORESOURCE_BUS;
|
|
dev_info(dev, " No bus range found for %pOF, using %pR\n",
|
|
dev_node, bus_range);
|
|
} else {
|
|
if (bus_range->end > bus_range->start + bus_max)
|
|
bus_range->end = bus_range->start + bus_max;
|
|
}
|
|
pci_add_resource(resources, bus_range);
|
|
|
|
/* Check for ranges property */
|
|
err = of_pci_range_parser_init(&parser, dev_node);
|
|
if (err)
|
|
return 0;
|
|
|
|
dev_dbg(dev, "Parsing ranges property...\n");
|
|
for_each_of_pci_range(&parser, &range) {
|
|
/* Read next ranges element */
|
|
if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO)
|
|
range_type = "IO";
|
|
else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM)
|
|
range_type = "MEM";
|
|
else
|
|
range_type = "err";
|
|
dev_info(dev, " %6s %#012llx..%#012llx -> %#012llx\n",
|
|
range_type, range.cpu_addr,
|
|
range.cpu_addr + range.size - 1, range.pci_addr);
|
|
|
|
/*
|
|
* If we failed translation or got a zero-sized region
|
|
* then skip this range
|
|
*/
|
|
if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
|
|
continue;
|
|
|
|
err = of_pci_range_to_resource(&range, dev_node, &tmp_res);
|
|
if (err)
|
|
continue;
|
|
|
|
res = devm_kmemdup(dev, &tmp_res, sizeof(tmp_res), GFP_KERNEL);
|
|
if (!res) {
|
|
err = -ENOMEM;
|
|
goto failed;
|
|
}
|
|
|
|
if (resource_type(res) == IORESOURCE_IO) {
|
|
if (!io_base) {
|
|
dev_err(dev, "I/O range found for %pOF. Please provide an io_base pointer to save CPU base address\n",
|
|
dev_node);
|
|
err = -EINVAL;
|
|
goto failed;
|
|
}
|
|
if (*io_base != (resource_size_t)OF_BAD_ADDR)
|
|
dev_warn(dev, "More than one I/O resource converted for %pOF. CPU base address for old range lost!\n",
|
|
dev_node);
|
|
*io_base = range.cpu_addr;
|
|
} else if (resource_type(res) == IORESOURCE_MEM) {
|
|
res->flags &= ~IORESOURCE_MEM_64;
|
|
}
|
|
|
|
pci_add_resource_offset(resources, res, res->start - range.pci_addr);
|
|
}
|
|
|
|
/* Check for dma-ranges property */
|
|
if (!ib_resources)
|
|
return 0;
|
|
err = of_pci_dma_range_parser_init(&parser, dev_node);
|
|
if (err)
|
|
return 0;
|
|
|
|
dev_dbg(dev, "Parsing dma-ranges property...\n");
|
|
for_each_of_pci_range(&parser, &range) {
|
|
/*
|
|
* If we failed translation or got a zero-sized region
|
|
* then skip this range
|
|
*/
|
|
if (((range.flags & IORESOURCE_TYPE_BITS) != IORESOURCE_MEM) ||
|
|
range.cpu_addr == OF_BAD_ADDR || range.size == 0)
|
|
continue;
|
|
|
|
dev_info(dev, " %6s %#012llx..%#012llx -> %#012llx\n",
|
|
"IB MEM", range.cpu_addr,
|
|
range.cpu_addr + range.size - 1, range.pci_addr);
|
|
|
|
|
|
err = of_pci_range_to_resource(&range, dev_node, &tmp_res);
|
|
if (err)
|
|
continue;
|
|
|
|
res = devm_kmemdup(dev, &tmp_res, sizeof(tmp_res), GFP_KERNEL);
|
|
if (!res) {
|
|
err = -ENOMEM;
|
|
goto failed;
|
|
}
|
|
|
|
pci_add_resource_offset(ib_resources, res,
|
|
res->start - range.pci_addr);
|
|
}
|
|
|
|
return 0;
|
|
|
|
failed:
|
|
pci_free_resource_list(resources);
|
|
return err;
|
|
}
|
|
|
|
#if IS_ENABLED(CONFIG_OF_IRQ)
|
|
/**
|
|
* of_irq_parse_pci - Resolve the interrupt for a PCI device
|
|
* @pdev: the device whose interrupt is to be resolved
|
|
* @out_irq: structure of_phandle_args filled by this function
|
|
*
|
|
* This function resolves the PCI interrupt for a given PCI device. If a
|
|
* device-node exists for a given pci_dev, it will use normal OF tree
|
|
* walking. If not, it will implement standard swizzling and walk up the
|
|
* PCI tree until an device-node is found, at which point it will finish
|
|
* resolving using the OF tree walking.
|
|
*/
|
|
static int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq)
|
|
{
|
|
struct device_node *dn, *ppnode = NULL;
|
|
struct pci_dev *ppdev;
|
|
__be32 laddr[3];
|
|
u8 pin;
|
|
int rc;
|
|
|
|
/*
|
|
* Check if we have a device node, if yes, fallback to standard
|
|
* device tree parsing
|
|
*/
|
|
dn = pci_device_to_OF_node(pdev);
|
|
if (dn) {
|
|
rc = of_irq_parse_one(dn, 0, out_irq);
|
|
if (!rc)
|
|
return rc;
|
|
}
|
|
|
|
/*
|
|
* Ok, we don't, time to have fun. Let's start by building up an
|
|
* interrupt spec. we assume #interrupt-cells is 1, which is standard
|
|
* for PCI. If you do different, then don't use that routine.
|
|
*/
|
|
rc = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin);
|
|
if (rc != 0)
|
|
goto err;
|
|
/* No pin, exit with no error message. */
|
|
if (pin == 0)
|
|
return -ENODEV;
|
|
|
|
/* Local interrupt-map in the device node? Use it! */
|
|
if (of_property_present(dn, "interrupt-map")) {
|
|
pin = pci_swizzle_interrupt_pin(pdev, pin);
|
|
ppnode = dn;
|
|
}
|
|
|
|
/* Now we walk up the PCI tree */
|
|
while (!ppnode) {
|
|
/* Get the pci_dev of our parent */
|
|
ppdev = pdev->bus->self;
|
|
|
|
/* Ouch, it's a host bridge... */
|
|
if (ppdev == NULL) {
|
|
ppnode = pci_bus_to_OF_node(pdev->bus);
|
|
|
|
/* No node for host bridge ? give up */
|
|
if (ppnode == NULL) {
|
|
rc = -EINVAL;
|
|
goto err;
|
|
}
|
|
} else {
|
|
/* We found a P2P bridge, check if it has a node */
|
|
ppnode = pci_device_to_OF_node(ppdev);
|
|
}
|
|
|
|
/*
|
|
* Ok, we have found a parent with a device-node, hand over to
|
|
* the OF parsing code.
|
|
* We build a unit address from the linux device to be used for
|
|
* resolution. Note that we use the linux bus number which may
|
|
* not match your firmware bus numbering.
|
|
* Fortunately, in most cases, interrupt-map-mask doesn't
|
|
* include the bus number as part of the matching.
|
|
* You should still be careful about that though if you intend
|
|
* to rely on this function (you ship a firmware that doesn't
|
|
* create device nodes for all PCI devices).
|
|
*/
|
|
if (ppnode)
|
|
break;
|
|
|
|
/*
|
|
* We can only get here if we hit a P2P bridge with no node;
|
|
* let's do standard swizzling and try again
|
|
*/
|
|
pin = pci_swizzle_interrupt_pin(pdev, pin);
|
|
pdev = ppdev;
|
|
}
|
|
|
|
out_irq->np = ppnode;
|
|
out_irq->args_count = 1;
|
|
out_irq->args[0] = pin;
|
|
laddr[0] = cpu_to_be32((pdev->bus->number << 16) | (pdev->devfn << 8));
|
|
laddr[1] = laddr[2] = cpu_to_be32(0);
|
|
rc = of_irq_parse_raw(laddr, out_irq);
|
|
if (rc)
|
|
goto err;
|
|
return 0;
|
|
err:
|
|
if (rc == -ENOENT) {
|
|
dev_warn(&pdev->dev,
|
|
"%s: no interrupt-map found, INTx interrupts not available\n",
|
|
__func__);
|
|
pr_warn_once("%s: possibly some PCI slots don't have level triggered interrupts capability\n",
|
|
__func__);
|
|
} else {
|
|
dev_err(&pdev->dev, "%s: failed with rc=%d\n", __func__, rc);
|
|
}
|
|
return rc;
|
|
}
|
|
|
|
/**
|
|
* of_irq_parse_and_map_pci() - Decode a PCI IRQ from the device tree and map to a VIRQ
|
|
* @dev: The PCI device needing an IRQ
|
|
* @slot: PCI slot number; passed when used as map_irq callback. Unused
|
|
* @pin: PCI IRQ pin number; passed when used as map_irq callback. Unused
|
|
*
|
|
* @slot and @pin are unused, but included in the function so that this
|
|
* function can be used directly as the map_irq callback to
|
|
* pci_assign_irq() and struct pci_host_bridge.map_irq pointer
|
|
*/
|
|
int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin)
|
|
{
|
|
struct of_phandle_args oirq;
|
|
int ret;
|
|
|
|
ret = of_irq_parse_pci(dev, &oirq);
|
|
if (ret)
|
|
return 0; /* Proper return code 0 == NO_IRQ */
|
|
|
|
return irq_create_of_mapping(&oirq);
|
|
}
|
|
EXPORT_SYMBOL_GPL(of_irq_parse_and_map_pci);
|
|
#endif /* CONFIG_OF_IRQ */
|
|
|
|
static int pci_parse_request_of_pci_ranges(struct device *dev,
|
|
struct pci_host_bridge *bridge)
|
|
{
|
|
int err, res_valid = 0;
|
|
resource_size_t iobase;
|
|
struct resource_entry *win, *tmp;
|
|
|
|
INIT_LIST_HEAD(&bridge->windows);
|
|
INIT_LIST_HEAD(&bridge->dma_ranges);
|
|
|
|
err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, &bridge->windows,
|
|
&bridge->dma_ranges, &iobase);
|
|
if (err)
|
|
return err;
|
|
|
|
err = devm_request_pci_bus_resources(dev, &bridge->windows);
|
|
if (err)
|
|
return err;
|
|
|
|
resource_list_for_each_entry_safe(win, tmp, &bridge->windows) {
|
|
struct resource *res = win->res;
|
|
|
|
switch (resource_type(res)) {
|
|
case IORESOURCE_IO:
|
|
err = devm_pci_remap_iospace(dev, res, iobase);
|
|
if (err) {
|
|
dev_warn(dev, "error %d: failed to map resource %pR\n",
|
|
err, res);
|
|
resource_list_destroy_entry(win);
|
|
}
|
|
break;
|
|
case IORESOURCE_MEM:
|
|
res_valid |= !(res->flags & IORESOURCE_PREFETCH);
|
|
|
|
if (!(res->flags & IORESOURCE_PREFETCH))
|
|
if (upper_32_bits(resource_size(res)))
|
|
dev_warn(dev, "Memory resource size exceeds max for 32 bits\n");
|
|
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!res_valid)
|
|
dev_warn(dev, "non-prefetchable memory resource required\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
|
|
{
|
|
if (!dev->of_node)
|
|
return 0;
|
|
|
|
bridge->swizzle_irq = pci_common_swizzle;
|
|
bridge->map_irq = of_irq_parse_and_map_pci;
|
|
|
|
return pci_parse_request_of_pci_ranges(dev, bridge);
|
|
}
|
|
|
|
#ifdef CONFIG_PCI_DYNAMIC_OF_NODES
|
|
|
|
void of_pci_remove_node(struct pci_dev *pdev)
|
|
{
|
|
struct device_node *np;
|
|
|
|
np = pci_device_to_OF_node(pdev);
|
|
if (!np || !of_node_check_flag(np, OF_DYNAMIC))
|
|
return;
|
|
pdev->dev.of_node = NULL;
|
|
|
|
of_changeset_revert(np->data);
|
|
of_changeset_destroy(np->data);
|
|
of_node_put(np);
|
|
}
|
|
|
|
void of_pci_make_dev_node(struct pci_dev *pdev)
|
|
{
|
|
struct device_node *ppnode, *np = NULL;
|
|
const char *pci_type;
|
|
struct of_changeset *cset;
|
|
const char *name;
|
|
int ret;
|
|
|
|
/*
|
|
* If there is already a device tree node linked to this device,
|
|
* return immediately.
|
|
*/
|
|
if (pci_device_to_OF_node(pdev))
|
|
return;
|
|
|
|
/* Check if there is device tree node for parent device */
|
|
if (!pdev->bus->self)
|
|
ppnode = pdev->bus->dev.of_node;
|
|
else
|
|
ppnode = pdev->bus->self->dev.of_node;
|
|
if (!ppnode)
|
|
return;
|
|
|
|
if (pci_is_bridge(pdev))
|
|
pci_type = "pci";
|
|
else
|
|
pci_type = "dev";
|
|
|
|
name = kasprintf(GFP_KERNEL, "%s@%x,%x", pci_type,
|
|
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
|
|
if (!name)
|
|
return;
|
|
|
|
cset = kmalloc(sizeof(*cset), GFP_KERNEL);
|
|
if (!cset)
|
|
goto out_free_name;
|
|
of_changeset_init(cset);
|
|
|
|
np = of_changeset_create_node(cset, ppnode, name);
|
|
if (!np)
|
|
goto out_destroy_cset;
|
|
|
|
ret = of_pci_add_properties(pdev, cset, np);
|
|
if (ret)
|
|
goto out_free_node;
|
|
|
|
ret = of_changeset_apply(cset);
|
|
if (ret)
|
|
goto out_free_node;
|
|
|
|
np->data = cset;
|
|
pdev->dev.of_node = np;
|
|
kfree(name);
|
|
|
|
return;
|
|
|
|
out_free_node:
|
|
of_node_put(np);
|
|
out_destroy_cset:
|
|
of_changeset_destroy(cset);
|
|
kfree(cset);
|
|
out_free_name:
|
|
kfree(name);
|
|
}
|
|
#endif
|
|
|
|
#endif /* CONFIG_PCI */
|
|
|
|
/**
|
|
* of_pci_get_max_link_speed - Find the maximum link speed of the given device node.
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* @node: Device tree node with the maximum link speed information.
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|
*
|
|
* This function will try to find the limitation of link speed by finding
|
|
* a property called "max-link-speed" of the given device node.
|
|
*
|
|
* Return:
|
|
* * > 0 - On success, a maximum link speed.
|
|
* * -EINVAL - Invalid "max-link-speed" property value, or failure to access
|
|
* the property of the device tree node.
|
|
*
|
|
* Returns the associated max link speed from DT, or a negative value if the
|
|
* required property is not found or is invalid.
|
|
*/
|
|
int of_pci_get_max_link_speed(struct device_node *node)
|
|
{
|
|
u32 max_link_speed;
|
|
|
|
if (of_property_read_u32(node, "max-link-speed", &max_link_speed) ||
|
|
max_link_speed == 0 || max_link_speed > 4)
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|
return -EINVAL;
|
|
|
|
return max_link_speed;
|
|
}
|
|
EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed);
|
|
|
|
/**
|
|
* of_pci_get_slot_power_limit - Parses the "slot-power-limit-milliwatt"
|
|
* property.
|
|
*
|
|
* @node: device tree node with the slot power limit information
|
|
* @slot_power_limit_value: pointer where the value should be stored in PCIe
|
|
* Slot Capabilities Register format
|
|
* @slot_power_limit_scale: pointer where the scale should be stored in PCIe
|
|
* Slot Capabilities Register format
|
|
*
|
|
* Returns the slot power limit in milliwatts and if @slot_power_limit_value
|
|
* and @slot_power_limit_scale pointers are non-NULL, fills in the value and
|
|
* scale in format used by PCIe Slot Capabilities Register.
|
|
*
|
|
* If the property is not found or is invalid, returns 0.
|
|
*/
|
|
u32 of_pci_get_slot_power_limit(struct device_node *node,
|
|
u8 *slot_power_limit_value,
|
|
u8 *slot_power_limit_scale)
|
|
{
|
|
u32 slot_power_limit_mw;
|
|
u8 value, scale;
|
|
|
|
if (of_property_read_u32(node, "slot-power-limit-milliwatt",
|
|
&slot_power_limit_mw))
|
|
slot_power_limit_mw = 0;
|
|
|
|
/* Calculate Slot Power Limit Value and Slot Power Limit Scale */
|
|
if (slot_power_limit_mw == 0) {
|
|
value = 0x00;
|
|
scale = 0;
|
|
} else if (slot_power_limit_mw <= 255) {
|
|
value = slot_power_limit_mw;
|
|
scale = 3;
|
|
} else if (slot_power_limit_mw <= 255*10) {
|
|
value = slot_power_limit_mw / 10;
|
|
scale = 2;
|
|
slot_power_limit_mw = slot_power_limit_mw / 10 * 10;
|
|
} else if (slot_power_limit_mw <= 255*100) {
|
|
value = slot_power_limit_mw / 100;
|
|
scale = 1;
|
|
slot_power_limit_mw = slot_power_limit_mw / 100 * 100;
|
|
} else if (slot_power_limit_mw <= 239*1000) {
|
|
value = slot_power_limit_mw / 1000;
|
|
scale = 0;
|
|
slot_power_limit_mw = slot_power_limit_mw / 1000 * 1000;
|
|
} else if (slot_power_limit_mw < 250*1000) {
|
|
value = 0xEF;
|
|
scale = 0;
|
|
slot_power_limit_mw = 239*1000;
|
|
} else if (slot_power_limit_mw <= 600*1000) {
|
|
value = 0xF0 + (slot_power_limit_mw / 1000 - 250) / 25;
|
|
scale = 0;
|
|
slot_power_limit_mw = slot_power_limit_mw / (1000*25) * (1000*25);
|
|
} else {
|
|
value = 0xFE;
|
|
scale = 0;
|
|
slot_power_limit_mw = 600*1000;
|
|
}
|
|
|
|
if (slot_power_limit_value)
|
|
*slot_power_limit_value = value;
|
|
|
|
if (slot_power_limit_scale)
|
|
*slot_power_limit_scale = scale;
|
|
|
|
return slot_power_limit_mw;
|
|
}
|
|
EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit);
|