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0c1945d336
This patch adds clock support for S5PV210. This patch adds the clock register definitions and the various system clocks in S5PV210. Clocks that are common to other S5P SoC'c are added in the common S5P clock support. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
455 lines
9.8 KiB
C
455 lines
9.8 KiB
C
/* linux/arch/arm/mach-s5pv210/clock.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5PV210 - Clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/sysdev.h>
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#include <linux/io.h>
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#include <mach/map.h>
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#include <plat/cpu-freq.h>
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#include <mach/regs-clock.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/pll.h>
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#include <plat/s5p-clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/s5pv210.h>
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static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
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}
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static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
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}
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static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
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}
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static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
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}
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static struct clk clk_h200 = {
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.name = "hclk200",
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.id = -1,
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};
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static struct clk clk_h100 = {
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.name = "hclk100",
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.id = -1,
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};
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static struct clk clk_h166 = {
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.name = "hclk166",
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.id = -1,
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};
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static struct clk clk_h133 = {
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.name = "hclk133",
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.id = -1,
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};
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static struct clk clk_p100 = {
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.name = "pclk100",
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.id = -1,
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};
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static struct clk clk_p83 = {
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.name = "pclk83",
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.id = -1,
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};
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static struct clk clk_p66 = {
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.name = "pclk66",
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.id = -1,
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};
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static struct clk *sys_clks[] = {
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&clk_h200,
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&clk_h100,
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&clk_h166,
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&clk_h133,
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&clk_p100,
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&clk_p83,
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&clk_p66
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};
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static struct clk init_clocks_disable[] = {
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{
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.name = "rot",
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.id = -1,
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.parent = &clk_h166,
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.enable = s5pv210_clk_ip0_ctrl,
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.ctrlbit = (1<<29),
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}, {
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.name = "otg",
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.id = -1,
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.parent = &clk_h133,
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.enable = s5pv210_clk_ip1_ctrl,
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.ctrlbit = (1<<16),
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}, {
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.name = "usb-host",
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.id = -1,
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.parent = &clk_h133,
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.enable = s5pv210_clk_ip1_ctrl,
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.ctrlbit = (1<<17),
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}, {
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.name = "lcd",
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.id = -1,
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.parent = &clk_h166,
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.enable = s5pv210_clk_ip1_ctrl,
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.ctrlbit = (1<<0),
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}, {
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.name = "cfcon",
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.id = 0,
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.parent = &clk_h133,
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.enable = s5pv210_clk_ip1_ctrl,
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.ctrlbit = (1<<25),
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}, {
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.name = "hsmmc",
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.id = 0,
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.parent = &clk_h133,
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.enable = s5pv210_clk_ip2_ctrl,
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.ctrlbit = (1<<16),
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}, {
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.name = "hsmmc",
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.id = 1,
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.parent = &clk_h133,
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.enable = s5pv210_clk_ip2_ctrl,
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.ctrlbit = (1<<17),
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}, {
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.name = "hsmmc",
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.id = 2,
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.parent = &clk_h133,
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.enable = s5pv210_clk_ip2_ctrl,
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.ctrlbit = (1<<18),
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}, {
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.name = "hsmmc",
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.id = 3,
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.parent = &clk_h133,
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.enable = s5pv210_clk_ip2_ctrl,
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.ctrlbit = (1<<19),
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}, {
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.name = "systimer",
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.id = -1,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<16),
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}, {
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.name = "watchdog",
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.id = -1,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<22),
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}, {
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.name = "rtc",
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.id = -1,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<15),
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}, {
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.name = "i2c",
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.id = 0,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<7),
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}, {
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.name = "i2c",
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.id = 1,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<8),
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}, {
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.name = "i2c",
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.id = 2,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<9),
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}, {
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.name = "spi",
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.id = 0,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<12),
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}, {
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.name = "spi",
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.id = 1,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<13),
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}, {
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.name = "spi",
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.id = 2,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<14),
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}, {
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.name = "timers",
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.id = -1,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<23),
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}, {
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.name = "adc",
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.id = -1,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<24),
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}, {
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.name = "keypad",
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.id = -1,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<21),
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}, {
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.name = "i2s_v50",
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.id = 0,
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.parent = &clk_p,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<4),
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}, {
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.name = "i2s_v32",
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.id = 0,
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.parent = &clk_p,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<4),
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}, {
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.name = "i2s_v32",
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.id = 1,
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.parent = &clk_p,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<4),
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}
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};
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static struct clk init_clocks[] = {
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{
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.name = "uart",
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.id = 0,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<7),
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}, {
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.name = "uart",
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.id = 1,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<8),
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}, {
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.name = "uart",
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.id = 2,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<9),
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}, {
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.name = "uart",
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.id = 3,
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.parent = &clk_p66,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1<<10),
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},
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};
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static struct clksrc_clk clk_mout_apll = {
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.clk = {
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.name = "mout_apll",
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.id = -1,
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},
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.sources = &clk_src_apll,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
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};
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static struct clksrc_clk clk_mout_epll = {
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.clk = {
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.name = "mout_epll",
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.id = -1,
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},
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.sources = &clk_src_epll,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
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};
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static struct clksrc_clk clk_mout_mpll = {
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.clk = {
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.name = "mout_mpll",
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.id = -1,
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},
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.sources = &clk_src_mpll,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
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};
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static struct clk *clkset_uart_list[] = {
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[6] = &clk_mout_mpll.clk,
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[7] = &clk_mout_epll.clk,
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};
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static struct clksrc_sources clkset_uart = {
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.sources = clkset_uart_list,
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.nr_sources = ARRAY_SIZE(clkset_uart_list),
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};
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static struct clksrc_clk clksrcs[] = {
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{
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.clk = {
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.name = "uclk1",
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.id = -1,
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.ctrlbit = (1<<17),
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.enable = s5pv210_clk_ip3_ctrl,
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},
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.sources = &clkset_uart,
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.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
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}
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};
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/* Clock initialisation code */
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static struct clksrc_clk *init_parents[] = {
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&clk_mout_apll,
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&clk_mout_epll,
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&clk_mout_mpll,
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};
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#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
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void __init_or_cpufreq s5pv210_setup_clocks(void)
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{
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struct clk *xtal_clk;
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unsigned long xtal;
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unsigned long armclk;
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unsigned long hclk200;
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unsigned long hclk166;
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unsigned long hclk133;
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unsigned long pclk100;
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unsigned long pclk83;
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unsigned long pclk66;
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unsigned long apll;
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unsigned long mpll;
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unsigned long epll;
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unsigned int ptr;
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u32 clkdiv0, clkdiv1;
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printk(KERN_DEBUG "%s: registering clocks\n", __func__);
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clkdiv0 = __raw_readl(S5P_CLK_DIV0);
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clkdiv1 = __raw_readl(S5P_CLK_DIV1);
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printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
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__func__, clkdiv0, clkdiv1);
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xtal_clk = clk_get(NULL, "xtal");
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BUG_ON(IS_ERR(xtal_clk));
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xtal = clk_get_rate(xtal_clk);
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clk_put(xtal_clk);
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printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
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apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
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mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
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epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
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printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld",
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apll, mpll, epll);
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armclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_APLL);
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if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX200_MASK)
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hclk200 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200);
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else
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hclk200 = armclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200);
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if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX166_MASK) {
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hclk166 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M);
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hclk166 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166);
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} else
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hclk166 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166);
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if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX133_MASK) {
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hclk133 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M);
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hclk133 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);
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} else
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hclk133 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);
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pclk100 = hclk200 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK100);
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pclk83 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83);
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pclk66 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66);
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printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld, \
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HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
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armclk, hclk200, hclk166, hclk133, pclk100, pclk83, pclk66);
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clk_fout_apll.rate = apll;
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clk_fout_mpll.rate = mpll;
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clk_fout_epll.rate = epll;
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clk_f.rate = armclk;
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clk_h.rate = hclk133;
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clk_p.rate = pclk66;
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clk_p66.rate = pclk66;
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clk_p83.rate = pclk83;
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clk_h133.rate = hclk133;
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clk_h166.rate = hclk166;
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clk_h200.rate = hclk200;
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for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
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s3c_set_clksrc(init_parents[ptr], true);
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for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
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s3c_set_clksrc(&clksrcs[ptr], true);
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}
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static struct clk *clks[] __initdata = {
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&clk_mout_epll.clk,
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&clk_mout_mpll.clk,
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};
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void __init s5pv210_register_clocks(void)
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{
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struct clk *clkp;
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int ret;
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int ptr;
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ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
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if (ret > 0)
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printk(KERN_ERR "Failed to register %u clocks\n", ret);
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s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
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s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
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ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks));
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if (ret > 0)
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printk(KERN_ERR "Failed to register system clocks\n");
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clkp = init_clocks_disable;
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for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
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ret = s3c24xx_register_clock(clkp);
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if (ret < 0) {
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printk(KERN_ERR "Failed to register clock %s (%d)\n",
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clkp->name, ret);
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}
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(clkp->enable)(clkp, 0);
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}
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s3c_pwmclk_init();
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}
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