linux/drivers/reset
Emil Renner Berthing b6d7406cd7 reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
We currently use 64bit I/O on the 32bit registers. This works because
there are an even number of assert and status registers, so they're only
ever accessed in pairs on 64bit boundaries.

There are however other reset controllers for audio and video on the
JH7100 SoC with only one status register that isn't 64bit aligned so
64bit I/O results in an unaligned access exception.

Switch to 32bit I/O in preparation for supporting these resets too.

Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05 15:44:07 +01:00
..
hisilicon reset: hi6220: Use the correct HiSilicon copyright 2021-06-07 10:44:38 +02:00
starfive reset: starfive: jh71x0: Use 32bit I/O on 32bit registers 2023-04-05 15:44:07 +01:00
sti reset: sti/syscfg: replace comma with semicolon 2021-05-10 09:41:43 +02:00
tegra reset: tegra-bpmp: Restore Handle errors in BPMP response 2022-04-04 11:14:13 +02:00
core.c reset: ACPI reset support 2022-05-03 17:41:25 +02:00
Kconfig reset: Create subdirectory for StarFive drivers 2023-04-05 15:43:49 +01:00
Makefile reset: Create subdirectory for StarFive drivers 2023-04-05 15:43:49 +01:00
reset-a10sr.c reset: a10sr: add missing of_match_table reference 2021-05-10 09:48:17 +02:00
reset-ath79.c
reset-axs10x.c
reset-bcm6345.c reset: bcm6345: Make reset_control_ops const 2021-05-10 09:40:03 +02:00
reset-berlin.c reset: berlin: support module build 2021-06-07 12:45:59 +02:00
reset-brcmstb-rescal.c reset: brcmstb-rescal: fix incorrect polarity of status bit 2021-10-05 10:48:56 +02:00
reset-brcmstb.c reset: brcmstb: Add missing MODULE_DEVICE_TABLE 2021-05-12 08:01:26 +02:00
reset-hsdk.c
reset-imx7.c reset: imx7: Fix the iMX8MP PCIe PHY PERST support 2022-08-30 16:28:48 +02:00
reset-intel-gw.c
reset-k210.c
reset-lantiq.c reset: lantiq: use devm_reset_controller_register() 2021-06-07 11:26:31 +02:00
reset-lpc18xx.c
reset-meson-audio-arb.c
reset-meson.c reset: reset-meson: add support for the Meson-S4 SoC Reset Controller 2022-05-03 17:40:51 +02:00
reset-microchip-sparx5.c reset: microchip-sparx5: issue a reset on startup 2022-08-30 16:29:41 +02:00
reset-mpfs.c reset: add polarfire soc reset support 2022-09-14 10:55:17 +03:00
reset-npcm.c reset: npcm: fix iprst2 and iprst4 setting 2022-09-22 17:48:35 +02:00
reset-oxnas.c reset: oxnas: replace file name with short description 2021-05-10 09:40:04 +02:00
reset-pistachio.c
reset-qcom-aoss.c
reset-qcom-pdc.c reset: qcom: Add PDC Global reset signals for WPSS 2021-07-21 12:16:17 +02:00
reset-raspberrypi.c
reset-rzg2l-usbphy-ctrl.c reset: renesas: Check return value of reset_control_deassert() 2022-04-04 11:00:27 +02:00
reset-scmi.c reset: reset-scmi: Port driver to the new scmi_reset_proto_ops interface 2021-03-30 16:34:54 +01:00
reset-simple.c reset: simple: Add AST2600 compatible 2022-05-03 17:40:51 +02:00
reset-socfpga.c reset: socfpga: add empty driver allowing consumers to probe 2021-10-05 12:23:16 +02:00
reset-sunplus.c reset: Add Sunplus SP7021 reset driver 2022-07-08 14:23:39 +02:00
reset-sunxi.c
reset-ti-sci.c treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_320.RULE 2022-06-10 14:51:36 +02:00
reset-ti-syscon.c treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_320.RULE 2022-06-10 14:51:36 +02:00
reset-tn48m.c reset: Add Delta TN48M CPLD reset controller 2022-02-25 09:59:35 +01:00
reset-tps380x.c reset: tps380x: Fix spelling mistake "Voltags" -> "Voltage" 2022-07-28 14:08:50 +02:00
reset-uniphier-glue.c reset: uniphier-glue: Fix possible null-ptr-deref 2023-01-03 11:30:46 +01:00
reset-uniphier.c reset: uniphier: Add NX1 reset support 2021-10-05 11:57:40 +02:00
reset-zynq.c
reset-zynqmp.c reset: reset-zynqmp: Fixed the argument data type 2021-08-23 12:55:18 +02:00