Martin Blumenstingl b609338b26 clk: meson: mpll: use 64bit math in rate_from_params ... On Meson8b the MPLL parent clock (fixed_pll) has a rate of 2550MHz. Multiplying this with SDM_DEN results in a value greater than 32bits. This is not a problem on the 64bit Meson GX SoCs, but it may result in undefined behavior on the older 32bit Meson8b SoC. While rate_from_params was only introduced recently to make the math reusable from _round_rate and _recalc_rate the original bug exists much longer. Fixes: 1c50da4f27 ("clk: meson: add mpll support") Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [as discussed on the ml, use DIV_ROUND_UP_ULL] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>		2017-04-07 17:45:30 +02:00
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clk-audio-divider.c	clk: meson: add audio clock divider support	2017-04-07 16:50:44 +02:00
clk-cpu.c	clk: meson8b: clean up cpu clocks	2016-06-22 18:02:35 -07:00
clk-mpll.c	clk: meson: mpll: use 64bit math in rate_from_params	2017-04-07 17:45:30 +02:00
clk-pll.c	clk: meson: Add support for parameters for specific PLLs	2017-04-04 12:05:12 -07:00
clkc.h	clk: meson: add audio clock divider support	2017-04-07 16:50:44 +02:00
gxbb-aoclk.c	clk: meson: Fix invalid use of sizeof in gxbb_aoclkc_probe()	2016-08-24 00:55:13 -07:00
gxbb.c	clk: meson: gxbb: add cts_i958 clock	2017-04-07 16:50:46 +02:00
gxbb.h	clk: meson: gxbb: add cts_i958 clock	2017-04-07 16:50:46 +02:00
Kconfig	clk: gxbb: add AmLogic GXBB clk controller driver	2016-06-22 18:07:31 -07:00
Makefile	clk: meson: add audio clock divider support	2017-04-07 16:50:44 +02:00
meson8b.c	clk: meson8b: add the mplls clocks 0, 1 and 2	2017-03-27 12:30:27 -07:00
meson8b.h	clk: meson8b: add the mplls clocks 0, 1 and 2	2017-03-27 12:30:27 -07:00