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b4f4372f96
So that we can profile code even in a local_irq_disable() section, only write 14 (instead of 15) into the %pil register to disable IRQs. This allows PIL level 15 to serve as a pseudo NMI. Signed-off-by: David S. Miller <davem@davemloft.net>
30 lines
1.0 KiB
C
30 lines
1.0 KiB
C
#ifndef _SPARC64_PIL_H
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#define _SPARC64_PIL_H
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/* To avoid some locking problems, we hard allocate certain PILs
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* for SMP cross call messages that must do a etrap/rtrap.
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*
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* A local_irq_disable() does not block the cross call delivery, so
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* when SMP locking is an issue we reschedule the event into a PIL
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* interrupt which is blocked by local_irq_disable().
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*
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* In fact any XCALL which has to etrap/rtrap has a problem because
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* it is difficult to prevent rtrap from running BH's, and that would
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* need to be done if the XCALL arrived while %pil==PIL_NORMAL_MAX.
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*
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* Finally, in order to handle profiling events even when a
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* local_irq_disable() is in progress, we only disable up to level 14
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* interrupts. Profile counter overflow interrupts arrive at level
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* 15.
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*/
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#define PIL_SMP_CALL_FUNC 1
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#define PIL_SMP_RECEIVE_SIGNAL 2
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#define PIL_SMP_CAPTURE 3
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#define PIL_SMP_CTX_NEW_VERSION 4
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#define PIL_DEVICE_IRQ 5
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#define PIL_SMP_CALL_FUNC_SNGL 6
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#define PIL_NORMAL_MAX 14
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#define PIL_NMI 15
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#endif /* !(_SPARC64_PIL_H) */
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