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98176380cb
Now that USB4 spec has names for these DP adapter registers we can use them instead. This makes it easier to match certain register to the spec. No functional changes. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
287 lines
7.3 KiB
C
287 lines
7.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Thunderbolt driver - Port/Switch config area registers
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*
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* Every thunderbolt device consists (logically) of a switch with multiple
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* ports. Every port contains up to four config regions (HOPS, PORT, SWITCH,
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* COUNTERS) which are used to configure the device.
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*
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* Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
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* Copyright (C) 2018, Intel Corporation
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*/
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#ifndef _TB_REGS
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#define _TB_REGS
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#include <linux/types.h>
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#define TB_ROUTE_SHIFT 8 /* number of bits in a port entry of a route */
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/*
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* TODO: should be 63? But we do not know how to receive frames larger than 256
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* bytes at the frame level. (header + checksum = 16, 60*4 = 240)
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*/
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#define TB_MAX_CONFIG_RW_LENGTH 60
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enum tb_switch_cap {
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TB_SWITCH_CAP_VSE = 0x05,
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};
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enum tb_switch_vse_cap {
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TB_VSE_CAP_PLUG_EVENTS = 0x01, /* also EEPROM */
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TB_VSE_CAP_TIME2 = 0x03,
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TB_VSE_CAP_IECS = 0x04,
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TB_VSE_CAP_LINK_CONTROLLER = 0x06, /* also IECS */
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};
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enum tb_port_cap {
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TB_PORT_CAP_PHY = 0x01,
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TB_PORT_CAP_TIME1 = 0x03,
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TB_PORT_CAP_ADAP = 0x04,
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TB_PORT_CAP_VSE = 0x05,
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};
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enum tb_port_state {
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TB_PORT_DISABLED = 0, /* tb_cap_phy.disable == 1 */
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TB_PORT_CONNECTING = 1, /* retry */
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TB_PORT_UP = 2,
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TB_PORT_UNPLUGGED = 7,
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};
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/* capability headers */
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struct tb_cap_basic {
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u8 next;
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/* enum tb_cap cap:8; prevent "narrower than values of its type" */
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u8 cap; /* if cap == 0x05 then we have a extended capability */
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} __packed;
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/**
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* struct tb_cap_extended_short - Switch extended short capability
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* @next: Pointer to the next capability. If @next and @length are zero
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* then we have a long cap.
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* @cap: Base capability ID (see &enum tb_switch_cap)
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* @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
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* @length: Length of this capability
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*/
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struct tb_cap_extended_short {
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u8 next;
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u8 cap;
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u8 vsec_id;
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u8 length;
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} __packed;
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/**
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* struct tb_cap_extended_long - Switch extended long capability
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* @zero1: This field should be zero
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* @cap: Base capability ID (see &enum tb_switch_cap)
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* @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
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* @zero2: This field should be zero
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* @next: Pointer to the next capability
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* @length: Length of this capability
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*/
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struct tb_cap_extended_long {
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u8 zero1;
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u8 cap;
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u8 vsec_id;
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u8 zero2;
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u16 next;
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u16 length;
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} __packed;
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/* capabilities */
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struct tb_cap_link_controller {
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struct tb_cap_extended_long cap_header;
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u32 count:4; /* number of link controllers */
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u32 unknown1:4;
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u32 base_offset:8; /*
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* offset (into this capability) of the configuration
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* area of the first link controller
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*/
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u32 length:12; /* link controller configuration area length */
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u32 unknown2:4; /* TODO check that length is correct */
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} __packed;
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struct tb_cap_phy {
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struct tb_cap_basic cap_header;
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u32 unknown1:16;
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u32 unknown2:14;
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bool disable:1;
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u32 unknown3:11;
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enum tb_port_state state:4;
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u32 unknown4:2;
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} __packed;
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struct tb_eeprom_ctl {
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bool clock:1; /* send pulse to transfer one bit */
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bool access_low:1; /* set to 0 before access */
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bool data_out:1; /* to eeprom */
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bool data_in:1; /* from eeprom */
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bool access_high:1; /* set to 1 before access */
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bool not_present:1; /* should be 0 */
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bool unknown1:1;
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bool present:1; /* should be 1 */
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u32 unknown2:24;
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} __packed;
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struct tb_cap_plug_events {
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struct tb_cap_extended_short cap_header;
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u32 __unknown1:2;
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u32 plug_events:5;
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u32 __unknown2:25;
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u32 __unknown3;
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u32 __unknown4;
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struct tb_eeprom_ctl eeprom_ctl;
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u32 __unknown5[7];
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u32 drom_offset; /* 32 bit register, but eeprom addresses are 16 bit */
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} __packed;
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/* device headers */
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/* Present on port 0 in TB_CFG_SWITCH at address zero. */
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struct tb_regs_switch_header {
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/* DWORD 0 */
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u16 vendor_id;
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u16 device_id;
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/* DWORD 1 */
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u32 first_cap_offset:8;
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u32 upstream_port_number:6;
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u32 max_port_number:6;
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u32 depth:3;
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u32 __unknown1:1;
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u32 revision:8;
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/* DWORD 2 */
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u32 route_lo;
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/* DWORD 3 */
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u32 route_hi:31;
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bool enabled:1;
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/* DWORD 4 */
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u32 plug_events_delay:8; /*
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* RW, pause between plug events in
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* milliseconds. Writing 0x00 is interpreted
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* as 255ms.
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*/
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u32 __unknown4:16;
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u32 thunderbolt_version:8;
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} __packed;
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enum tb_port_type {
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TB_TYPE_INACTIVE = 0x000000,
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TB_TYPE_PORT = 0x000001,
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TB_TYPE_NHI = 0x000002,
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/* TB_TYPE_ETHERNET = 0x020000, lower order bits are not known */
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/* TB_TYPE_SATA = 0x080000, lower order bits are not known */
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TB_TYPE_DP_HDMI_IN = 0x0e0101,
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TB_TYPE_DP_HDMI_OUT = 0x0e0102,
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TB_TYPE_PCIE_DOWN = 0x100101,
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TB_TYPE_PCIE_UP = 0x100102,
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/* TB_TYPE_USB = 0x200000, lower order bits are not known */
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};
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/* Present on every port in TB_CF_PORT at address zero. */
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struct tb_regs_port_header {
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/* DWORD 0 */
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u16 vendor_id;
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u16 device_id;
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/* DWORD 1 */
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u32 first_cap_offset:8;
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u32 max_counters:11;
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u32 __unknown1:5;
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u32 revision:8;
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/* DWORD 2 */
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enum tb_port_type type:24;
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u32 thunderbolt_version:8;
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/* DWORD 3 */
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u32 __unknown2:20;
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u32 port_number:6;
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u32 __unknown3:6;
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/* DWORD 4 */
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u32 nfc_credits;
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/* DWORD 5 */
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u32 max_in_hop_id:11;
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u32 max_out_hop_id:11;
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u32 __unknown4:10;
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/* DWORD 6 */
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u32 __unknown5;
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/* DWORD 7 */
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u32 __unknown6;
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} __packed;
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/* Basic adapter configuration registers */
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#define ADP_CS_4 0x04
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#define ADP_CS_4_NFC_BUFFERS_MASK GENMASK(9, 0)
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#define ADP_CS_4_TOTAL_BUFFERS_MASK GENMASK(29, 20)
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#define ADP_CS_4_TOTAL_BUFFERS_SHIFT 20
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#define ADP_CS_5 0x05
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#define ADP_CS_5_LCA_MASK GENMASK(28, 22)
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#define ADP_CS_5_LCA_SHIFT 22
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/* Display Port adapter registers */
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#define ADP_DP_CS_0 0x00
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#define ADP_DP_CS_0_VIDEO_HOPID_MASK GENMASK(26, 16)
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#define ADP_DP_CS_0_VIDEO_HOPID_SHIFT 16
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#define ADP_DP_CS_0_AE BIT(30)
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#define ADP_DP_CS_0_VE BIT(31)
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#define ADP_DP_CS_1_AUX_TX_HOPID_MASK GENMASK(10, 0)
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#define ADP_DP_CS_1_AUX_RX_HOPID_MASK GENMASK(21, 11)
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#define ADP_DP_CS_1_AUX_RX_HOPID_SHIFT 11
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#define ADP_DP_CS_2 0x02
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#define ADP_DP_CS_2_HDP BIT(6)
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#define ADP_DP_CS_3 0x03
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#define ADP_DP_CS_3_HDPC BIT(9)
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#define DP_LOCAL_CAP 0x04
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#define DP_REMOTE_CAP 0x05
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/* PCIe adapter registers */
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#define ADP_PCIE_CS_0 0x00
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#define ADP_PCIE_CS_0_PE BIT(31)
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/* Hop register from TB_CFG_HOPS. 8 byte per entry. */
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struct tb_regs_hop {
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/* DWORD 0 */
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u32 next_hop:11; /*
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* hop to take after sending the packet through
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* out_port (on the incoming port of the next switch)
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*/
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u32 out_port:6; /* next port of the path (on the same switch) */
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u32 initial_credits:8;
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u32 unknown1:6; /* set to zero */
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bool enable:1;
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/* DWORD 1 */
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u32 weight:4;
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u32 unknown2:4; /* set to zero */
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u32 priority:3;
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bool drop_packages:1;
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u32 counter:11; /* index into TB_CFG_COUNTERS on this port */
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bool counter_enable:1;
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bool ingress_fc:1;
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bool egress_fc:1;
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bool ingress_shared_buffer:1;
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bool egress_shared_buffer:1;
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bool pending:1;
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u32 unknown3:3; /* set to zero */
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} __packed;
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/* Common link controller registers */
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#define TB_LC_DESC 0x02
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#define TB_LC_DESC_NLC_MASK GENMASK(3, 0)
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#define TB_LC_DESC_SIZE_SHIFT 8
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#define TB_LC_DESC_SIZE_MASK GENMASK(15, 8)
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#define TB_LC_DESC_PORT_SIZE_SHIFT 16
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#define TB_LC_DESC_PORT_SIZE_MASK GENMASK(27, 16)
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#define TB_LC_FUSE 0x03
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/* Link controller registers */
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#define TB_LC_SX_CTRL 0x96
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#define TB_LC_SX_CTRL_L1C BIT(16)
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#define TB_LC_SX_CTRL_L2C BIT(20)
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#define TB_LC_SX_CTRL_UPSTREAM BIT(30)
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#define TB_LC_SX_CTRL_SLP BIT(31)
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#endif
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