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4d0642074c
TMU Version 1 has 4 TTRCRs, while TMU Version >=2 has 16 TTRCRs.
So limit the len to 4 will report "invalid range data" for i.MX93.
This patch drop the local array with allocated ttrcr array and
able to support larger tmu ranges.
Fixes: f12d60c81f
("thermal/drivers/qoriq: Support version 2.1")
Tested-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20240226003657.3012880-1-peng.fan@oss.nxp.com
400 lines
9.8 KiB
C
400 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright 2016 Freescale Semiconductor, Inc.
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/sizes.h>
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#include <linux/thermal.h>
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#include <linux/units.h>
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#include "thermal_hwmon.h"
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#define SITES_MAX 16
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#define TMR_DISABLE 0x0
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#define TMR_ME 0x80000000
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#define TMR_ALPF 0x0c000000
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#define TMR_ALPF_V2 0x03000000
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#define TMTMIR_DEFAULT 0x0000000f
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#define TIER_DISABLE 0x0
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#define TEUMR0_V2 0x51009c00
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#define TMSARA_V2 0xe
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#define TMU_VER1 0x1
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#define TMU_VER2 0x2
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#define REGS_TMR 0x000 /* Mode Register */
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#define TMR_DISABLE 0x0
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#define TMR_ME 0x80000000
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#define TMR_ALPF 0x0c000000
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#define REGS_TMTMIR 0x008 /* Temperature measurement interval Register */
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#define TMTMIR_DEFAULT 0x0000000f
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#define REGS_V2_TMSR 0x008 /* monitor site register */
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#define REGS_V2_TMTMIR 0x00c /* Temperature measurement interval Register */
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#define REGS_TIER 0x020 /* Interrupt Enable Register */
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#define TIER_DISABLE 0x0
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#define REGS_TTCFGR 0x080 /* Temperature Configuration Register */
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#define REGS_TSCFGR 0x084 /* Sensor Configuration Register */
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#define REGS_TRITSR(n) (0x100 + 16 * (n)) /* Immediate Temperature
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* Site Register
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*/
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#define TRITSR_V BIT(31)
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#define TRITSR_TP5 BIT(9)
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#define REGS_V2_TMSAR(n) (0x304 + 16 * (n)) /* TMU monitoring
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* site adjustment register
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*/
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#define REGS_TTRnCR(n) (0xf10 + 4 * (n)) /* Temperature Range n
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* Control Register
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*/
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#define NUM_TTRCR_V1 4
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#define NUM_TTRCR_MAX 16
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#define REGS_IPBRR(n) (0xbf8 + 4 * (n)) /* IP Block Revision
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* Register n
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*/
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#define REGS_V2_TEUMR(n) (0xf00 + 4 * (n))
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/*
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* Thermal zone data
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*/
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struct qoriq_sensor {
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int id;
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};
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struct qoriq_tmu_data {
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int ver;
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u32 ttrcr[NUM_TTRCR_MAX];
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struct regmap *regmap;
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struct clk *clk;
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struct qoriq_sensor sensor[SITES_MAX];
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};
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static struct qoriq_tmu_data *qoriq_sensor_to_data(struct qoriq_sensor *s)
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{
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return container_of(s, struct qoriq_tmu_data, sensor[s->id]);
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}
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static int tmu_get_temp(struct thermal_zone_device *tz, int *temp)
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{
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struct qoriq_sensor *qsensor = thermal_zone_device_priv(tz);
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struct qoriq_tmu_data *qdata = qoriq_sensor_to_data(qsensor);
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u32 val;
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/*
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* REGS_TRITSR(id) has the following layout:
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*
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* For TMU Rev1:
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* 31 ... 7 6 5 4 3 2 1 0
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* V TEMP
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*
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* Where V bit signifies if the measurement is ready and is
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* within sensor range. TEMP is an 8 bit value representing
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* temperature in Celsius.
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* For TMU Rev2:
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* 31 ... 8 7 6 5 4 3 2 1 0
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* V TEMP
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*
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* Where V bit signifies if the measurement is ready and is
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* within sensor range. TEMP is an 9 bit value representing
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* temperature in KelVin.
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*/
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regmap_read(qdata->regmap, REGS_TMR, &val);
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if (!(val & TMR_ME))
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return -EAGAIN;
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if (regmap_read_poll_timeout(qdata->regmap,
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REGS_TRITSR(qsensor->id),
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val,
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val & TRITSR_V,
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USEC_PER_MSEC,
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10 * USEC_PER_MSEC))
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return -ENODATA;
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if (qdata->ver == TMU_VER1) {
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*temp = (val & GENMASK(7, 0)) * MILLIDEGREE_PER_DEGREE;
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} else {
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if (val & TRITSR_TP5)
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*temp = milli_kelvin_to_millicelsius((val & GENMASK(8, 0)) *
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MILLIDEGREE_PER_DEGREE + 500);
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else
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*temp = kelvin_to_millicelsius(val & GENMASK(8, 0));
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}
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return 0;
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}
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static const struct thermal_zone_device_ops tmu_tz_ops = {
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.get_temp = tmu_get_temp,
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};
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static int qoriq_tmu_register_tmu_zone(struct device *dev,
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struct qoriq_tmu_data *qdata)
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{
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int id, sites = 0;
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for (id = 0; id < SITES_MAX; id++) {
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struct thermal_zone_device *tzd;
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struct qoriq_sensor *sensor = &qdata->sensor[id];
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int ret;
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sensor->id = id;
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tzd = devm_thermal_of_zone_register(dev, id,
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sensor,
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&tmu_tz_ops);
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ret = PTR_ERR_OR_ZERO(tzd);
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if (ret) {
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if (ret == -ENODEV)
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continue;
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return ret;
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}
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if (qdata->ver == TMU_VER1)
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sites |= 0x1 << (15 - id);
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else
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sites |= 0x1 << id;
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devm_thermal_add_hwmon_sysfs(dev, tzd);
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}
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if (sites) {
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if (qdata->ver == TMU_VER1) {
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regmap_write(qdata->regmap, REGS_TMR, TMR_ME | TMR_ALPF | sites);
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} else {
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regmap_write(qdata->regmap, REGS_V2_TMSR, sites);
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regmap_write(qdata->regmap, REGS_TMR, TMR_ME | TMR_ALPF_V2);
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}
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}
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return 0;
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}
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static int qoriq_tmu_calibration(struct device *dev,
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struct qoriq_tmu_data *data)
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{
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int i, val, len;
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const u32 *calibration;
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struct device_node *np = dev->of_node;
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len = of_property_count_u32_elems(np, "fsl,tmu-range");
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if (len < 0 || (data->ver == TMU_VER1 && len > NUM_TTRCR_V1) ||
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(data->ver > TMU_VER1 && len > NUM_TTRCR_MAX)) {
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dev_err(dev, "invalid range data.\n");
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return len;
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}
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val = of_property_read_u32_array(np, "fsl,tmu-range", data->ttrcr, len);
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if (val != 0) {
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dev_err(dev, "failed to read range data.\n");
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return val;
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}
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/* Init temperature range registers */
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for (i = 0; i < len; i++)
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regmap_write(data->regmap, REGS_TTRnCR(i), data->ttrcr[i]);
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calibration = of_get_property(np, "fsl,tmu-calibration", &len);
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if (calibration == NULL || len % 8) {
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dev_err(dev, "invalid calibration data.\n");
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return -ENODEV;
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}
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for (i = 0; i < len; i += 8, calibration += 2) {
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val = of_read_number(calibration, 1);
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regmap_write(data->regmap, REGS_TTCFGR, val);
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val = of_read_number(calibration + 1, 1);
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regmap_write(data->regmap, REGS_TSCFGR, val);
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}
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return 0;
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}
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static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
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{
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/* Disable interrupt, using polling instead */
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regmap_write(data->regmap, REGS_TIER, TIER_DISABLE);
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/* Set update_interval */
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if (data->ver == TMU_VER1) {
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regmap_write(data->regmap, REGS_TMTMIR, TMTMIR_DEFAULT);
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} else {
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regmap_write(data->regmap, REGS_V2_TMTMIR, TMTMIR_DEFAULT);
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regmap_write(data->regmap, REGS_V2_TEUMR(0), TEUMR0_V2);
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}
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/* Disable monitoring */
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regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
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}
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static const struct regmap_range qoriq_yes_ranges[] = {
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regmap_reg_range(REGS_TMR, REGS_TSCFGR),
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regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(15)),
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regmap_reg_range(REGS_V2_TEUMR(0), REGS_V2_TEUMR(2)),
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regmap_reg_range(REGS_V2_TMSAR(0), REGS_V2_TMSAR(15)),
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regmap_reg_range(REGS_IPBRR(0), REGS_IPBRR(1)),
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/* Read only registers below */
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regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)),
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};
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static const struct regmap_access_table qoriq_wr_table = {
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.yes_ranges = qoriq_yes_ranges,
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.n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges) - 1,
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};
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static const struct regmap_access_table qoriq_rd_table = {
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.yes_ranges = qoriq_yes_ranges,
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.n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges),
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};
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static void qoriq_tmu_action(void *p)
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{
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struct qoriq_tmu_data *data = p;
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regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
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clk_disable_unprepare(data->clk);
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}
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static int qoriq_tmu_probe(struct platform_device *pdev)
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{
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int ret;
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u32 ver;
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struct qoriq_tmu_data *data;
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struct device_node *np = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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const bool little_endian = of_property_read_bool(np, "little-endian");
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const enum regmap_endian format_endian =
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little_endian ? REGMAP_ENDIAN_LITTLE : REGMAP_ENDIAN_BIG;
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const struct regmap_config regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.rd_table = &qoriq_rd_table,
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.wr_table = &qoriq_wr_table,
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.val_format_endian = format_endian,
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.max_register = SZ_4K,
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};
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void __iomem *base;
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data = devm_kzalloc(dev, sizeof(struct qoriq_tmu_data),
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GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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base = devm_platform_ioremap_resource(pdev, 0);
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ret = PTR_ERR_OR_ZERO(base);
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if (ret) {
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dev_err(dev, "Failed to get memory region\n");
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return ret;
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}
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data->regmap = devm_regmap_init_mmio(dev, base, ®map_config);
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ret = PTR_ERR_OR_ZERO(data->regmap);
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if (ret) {
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dev_err(dev, "Failed to init regmap (%d)\n", ret);
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return ret;
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}
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data->clk = devm_clk_get_optional(dev, NULL);
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if (IS_ERR(data->clk))
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return PTR_ERR(data->clk);
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ret = clk_prepare_enable(data->clk);
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if (ret) {
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dev_err(dev, "Failed to enable clock\n");
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return ret;
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}
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ret = devm_add_action_or_reset(dev, qoriq_tmu_action, data);
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if (ret)
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return ret;
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/* version register offset at: 0xbf8 on both v1 and v2 */
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ret = regmap_read(data->regmap, REGS_IPBRR(0), &ver);
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if (ret) {
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dev_err(&pdev->dev, "Failed to read IP block version\n");
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return ret;
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}
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data->ver = (ver >> 8) & 0xff;
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qoriq_tmu_init_device(data); /* TMU initialization */
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ret = qoriq_tmu_calibration(dev, data); /* TMU calibration */
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if (ret < 0)
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return ret;
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ret = qoriq_tmu_register_tmu_zone(dev, data);
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if (ret < 0) {
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dev_err(dev, "Failed to register sensors\n");
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return ret;
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}
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platform_set_drvdata(pdev, data);
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return 0;
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}
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static int __maybe_unused qoriq_tmu_suspend(struct device *dev)
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{
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struct qoriq_tmu_data *data = dev_get_drvdata(dev);
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int ret;
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ret = regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, 0);
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if (ret)
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return ret;
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clk_disable_unprepare(data->clk);
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return 0;
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}
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static int __maybe_unused qoriq_tmu_resume(struct device *dev)
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{
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int ret;
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struct qoriq_tmu_data *data = dev_get_drvdata(dev);
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ret = clk_prepare_enable(data->clk);
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if (ret)
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return ret;
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/* Enable monitoring */
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return regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, TMR_ME);
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}
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static SIMPLE_DEV_PM_OPS(qoriq_tmu_pm_ops,
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qoriq_tmu_suspend, qoriq_tmu_resume);
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static const struct of_device_id qoriq_tmu_match[] = {
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{ .compatible = "fsl,qoriq-tmu", },
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{ .compatible = "fsl,imx8mq-tmu", },
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{},
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};
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MODULE_DEVICE_TABLE(of, qoriq_tmu_match);
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static struct platform_driver qoriq_tmu = {
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.driver = {
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.name = "qoriq_thermal",
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.pm = &qoriq_tmu_pm_ops,
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.of_match_table = qoriq_tmu_match,
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},
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.probe = qoriq_tmu_probe,
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};
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module_platform_driver(qoriq_tmu);
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MODULE_AUTHOR("Jia Hongtao <hongtao.jia@nxp.com>");
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MODULE_DESCRIPTION("QorIQ Thermal Monitoring Unit driver");
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MODULE_LICENSE("GPL v2");
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