mirror of
https://github.com/torvalds/linux.git
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dcf30fc0ca
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200708165856.15322-1-grandmaster@al2klimov.de
166 lines
4.2 KiB
C
166 lines
4.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/**
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* timer-ti-32k.c - OMAP2 32k Timer Support
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*
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* Copyright (C) 2009 Nokia Corporation
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*
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* Update to use new clocksource/clockevent layers
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* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
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* Copyright (C) 2007 MontaVista Software, Inc.
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*
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* Original driver:
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* Copyright (C) 2005 Nokia Corporation
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* Author: Paul Mundt <paul.mundt@nokia.com>
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* Juha Yrjölä <juha.yrjola@nokia.com>
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* OMAP Dual-mode timer framework support by Timo Teras
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*
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* Some parts based off of TI's 24xx code:
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*
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* Copyright (C) 2004-2009 Texas Instruments, Inc.
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*
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* Roughly modelled after the OMAP1 MPU timer code.
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
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*/
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#include <linux/clk.h>
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#include <linux/init.h>
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#include <linux/time.h>
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#include <linux/sched_clock.h>
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#include <linux/clocksource.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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/*
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* 32KHz clocksource ... always available, on pretty most chips except
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* OMAP 730 and 1510. Other timers could be used as clocksources, with
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* higher resolution in free-running counter modes (e.g. 12 MHz xtal),
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* but systems won't necessarily want to spend resources that way.
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*/
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#define OMAP2_32KSYNCNT_REV_OFF 0x0
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#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
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#define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10
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#define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30
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struct ti_32k {
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void __iomem *base;
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void __iomem *counter;
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struct clocksource cs;
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};
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static inline struct ti_32k *to_ti_32k(struct clocksource *cs)
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{
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return container_of(cs, struct ti_32k, cs);
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}
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static u64 notrace ti_32k_read_cycles(struct clocksource *cs)
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{
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struct ti_32k *ti = to_ti_32k(cs);
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return (u64)readl_relaxed(ti->counter);
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}
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static struct ti_32k ti_32k_timer = {
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.cs = {
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.name = "32k_counter",
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.rating = 250,
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.read = ti_32k_read_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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},
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};
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static u64 notrace omap_32k_read_sched_clock(void)
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{
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return ti_32k_read_cycles(&ti_32k_timer.cs);
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}
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static void __init ti_32k_timer_enable_clock(struct device_node *np,
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const char *name)
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{
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struct clk *clock;
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int error;
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clock = of_clk_get_by_name(np->parent, name);
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if (IS_ERR(clock)) {
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/* Only some SoCs have a separate interface clock */
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if (PTR_ERR(clock) == -EINVAL && !strncmp("ick", name, 3))
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return;
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pr_warn("%s: could not get clock %s %li\n",
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__func__, name, PTR_ERR(clock));
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return;
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}
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error = clk_prepare_enable(clock);
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if (error) {
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pr_warn("%s: could not enable %s: %i\n",
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__func__, name, error);
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return;
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}
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}
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static void __init ti_32k_timer_module_init(struct device_node *np,
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void __iomem *base)
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{
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void __iomem *sysc = base + 4;
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if (!of_device_is_compatible(np->parent, "ti,sysc"))
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return;
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ti_32k_timer_enable_clock(np, "fck");
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ti_32k_timer_enable_clock(np, "ick");
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/*
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* Force idle module as wkup domain is active with MPU.
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* No need to tag the module disabled for ti-sysc probe.
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*/
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writel_relaxed(0, sysc);
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}
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static int __init ti_32k_timer_init(struct device_node *np)
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{
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int ret;
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ti_32k_timer.base = of_iomap(np, 0);
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if (!ti_32k_timer.base) {
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pr_err("Can't ioremap 32k timer base\n");
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return -ENXIO;
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}
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if (!of_machine_is_compatible("ti,am43"))
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ti_32k_timer.cs.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
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ti_32k_timer.counter = ti_32k_timer.base;
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ti_32k_timer_module_init(np, ti_32k_timer.base);
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/*
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* 32k sync Counter IP register offsets vary between the highlander
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* version and the legacy ones.
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*
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* The 'SCHEME' bits(30-31) of the revision register is used to identify
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* the version.
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*/
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if (readl_relaxed(ti_32k_timer.base + OMAP2_32KSYNCNT_REV_OFF) &
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OMAP2_32KSYNCNT_REV_SCHEME)
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ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_HIGH;
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else
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ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_LOW;
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pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
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ret = clocksource_register_hz(&ti_32k_timer.cs, 32768);
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if (ret) {
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pr_err("32k_counter: can't register clocksource\n");
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return ret;
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}
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sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
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return 0;
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}
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TIMER_OF_DECLARE(ti_32k_timer, "ti,omap-counter32k",
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ti_32k_timer_init);
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