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6faadbbb7f
... and __initconst if applicable. Based on similar work for an older kernel in the Grsecurity patch. [JD: fix toshiba-wmi build] [JD: add htcpen] [JD: move __initconst where checkscript wants it] Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Jean Delvare <jdelvare@suse.de>
378 lines
11 KiB
C
378 lines
11 KiB
C
/*
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* Copyright (c) 2016 Mellanox Technologies. All rights reserved.
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* Copyright (c) 2016 Vadim Pasternak <vadimp@mellanox.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the names of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/device.h>
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#include <linux/dmi.h>
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#include <linux/i2c.h>
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#include <linux/i2c-mux.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/i2c-mux-reg.h>
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#include <linux/platform_data/mlxcpld-hotplug.h>
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#define MLX_PLAT_DEVICE_NAME "mlxplat"
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/* LPC bus IO offsets */
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#define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000
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#define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500
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#define MLXPLAT_CPLD_LPC_REG_AGGR_ADRR 0x253a
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#define MLXPLAT_CPLD_LPC_REG_PSU_ADRR 0x2558
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#define MLXPLAT_CPLD_LPC_REG_PWR_ADRR 0x2564
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#define MLXPLAT_CPLD_LPC_REG_FAN_ADRR 0x2588
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#define MLXPLAT_CPLD_LPC_IO_RANGE 0x100
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#define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb
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#define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda
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#define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL
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#define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
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MLXPLAT_CPLD_LPC_I2C_CH1_OFF) | \
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MLXPLAT_CPLD_LPC_PIO_OFFSET)
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#define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \
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MLXPLAT_CPLD_LPC_I2C_CH2_OFF) | \
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MLXPLAT_CPLD_LPC_PIO_OFFSET)
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/* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */
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#define MLXPLAT_CPLD_AGGR_PSU_MASK_DEF 0x08
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#define MLXPLAT_CPLD_AGGR_PWR_MASK_DEF 0x08
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#define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40
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#define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \
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MLXPLAT_CPLD_AGGR_FAN_MASK_DEF)
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#define MLXPLAT_CPLD_AGGR_MASK_MSN21XX 0x04
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#define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0)
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#define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0)
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#define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0)
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/* Start channel numbers */
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#define MLXPLAT_CPLD_CH1 2
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#define MLXPLAT_CPLD_CH2 10
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/* Number of LPC attached MUX platform devices */
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#define MLXPLAT_CPLD_LPC_MUX_DEVS 2
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/* mlxplat_priv - platform private data
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* @pdev_i2c - i2c controller platform device
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* @pdev_mux - array of mux platform devices
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*/
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struct mlxplat_priv {
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struct platform_device *pdev_i2c;
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struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS];
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struct platform_device *pdev_hotplug;
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};
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/* Regions for LPC I2C controller and LPC base register space */
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static const struct resource mlxplat_lpc_resources[] = {
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[0] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_I2C_BASE_ADRR,
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MLXPLAT_CPLD_LPC_IO_RANGE,
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"mlxplat_cpld_lpc_i2c_ctrl", IORESOURCE_IO),
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[1] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_REG_BASE_ADRR,
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MLXPLAT_CPLD_LPC_IO_RANGE,
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"mlxplat_cpld_lpc_regs",
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IORESOURCE_IO),
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};
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/* Platform default channels */
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static const int mlxplat_default_channels[][8] = {
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{
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MLXPLAT_CPLD_CH1, MLXPLAT_CPLD_CH1 + 1, MLXPLAT_CPLD_CH1 + 2,
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MLXPLAT_CPLD_CH1 + 3, MLXPLAT_CPLD_CH1 + 4, MLXPLAT_CPLD_CH1 +
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5, MLXPLAT_CPLD_CH1 + 6, MLXPLAT_CPLD_CH1 + 7
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},
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{
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MLXPLAT_CPLD_CH2, MLXPLAT_CPLD_CH2 + 1, MLXPLAT_CPLD_CH2 + 2,
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MLXPLAT_CPLD_CH2 + 3, MLXPLAT_CPLD_CH2 + 4, MLXPLAT_CPLD_CH2 +
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5, MLXPLAT_CPLD_CH2 + 6, MLXPLAT_CPLD_CH2 + 7
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},
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};
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/* Platform channels for MSN21xx system family */
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static const int mlxplat_msn21xx_channels[] = { 1, 2, 3, 4, 5, 6, 7, 8 };
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/* Platform mux data */
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static struct i2c_mux_reg_platform_data mlxplat_mux_data[] = {
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{
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.parent = 1,
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.base_nr = MLXPLAT_CPLD_CH1,
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.write_only = 1,
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.reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1,
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.reg_size = 1,
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.idle_in_use = 1,
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},
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{
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.parent = 1,
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.base_nr = MLXPLAT_CPLD_CH2,
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.write_only = 1,
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.reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2,
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.reg_size = 1,
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.idle_in_use = 1,
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},
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};
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/* Platform hotplug devices */
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static struct mlxcpld_hotplug_device mlxplat_mlxcpld_psu[] = {
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{
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.brdinfo = { I2C_BOARD_INFO("24c02", 0x51) },
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.bus = 10,
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},
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{
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.brdinfo = { I2C_BOARD_INFO("24c02", 0x50) },
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.bus = 10,
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},
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};
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static struct mlxcpld_hotplug_device mlxplat_mlxcpld_pwr[] = {
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{
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.brdinfo = { I2C_BOARD_INFO("dps460", 0x59) },
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.bus = 10,
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},
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{
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.brdinfo = { I2C_BOARD_INFO("dps460", 0x58) },
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.bus = 10,
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},
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};
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static struct mlxcpld_hotplug_device mlxplat_mlxcpld_fan[] = {
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{
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.brdinfo = { I2C_BOARD_INFO("24c32", 0x50) },
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.bus = 11,
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},
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{
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.brdinfo = { I2C_BOARD_INFO("24c32", 0x50) },
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.bus = 12,
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},
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{
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.brdinfo = { I2C_BOARD_INFO("24c32", 0x50) },
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.bus = 13,
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},
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{
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.brdinfo = { I2C_BOARD_INFO("24c32", 0x50) },
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.bus = 14,
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},
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};
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/* Platform hotplug default data */
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static
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struct mlxcpld_hotplug_platform_data mlxplat_mlxcpld_default_data = {
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.top_aggr_offset = MLXPLAT_CPLD_LPC_REG_AGGR_ADRR,
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.top_aggr_mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
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.top_aggr_psu_mask = MLXPLAT_CPLD_AGGR_PSU_MASK_DEF,
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.psu_reg_offset = MLXPLAT_CPLD_LPC_REG_PSU_ADRR,
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.psu_mask = MLXPLAT_CPLD_PSU_MASK,
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.psu_count = ARRAY_SIZE(mlxplat_mlxcpld_psu),
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.psu = mlxplat_mlxcpld_psu,
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.top_aggr_pwr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF,
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.pwr_reg_offset = MLXPLAT_CPLD_LPC_REG_PWR_ADRR,
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.pwr_mask = MLXPLAT_CPLD_PWR_MASK,
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.pwr_count = ARRAY_SIZE(mlxplat_mlxcpld_pwr),
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.pwr = mlxplat_mlxcpld_pwr,
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.top_aggr_fan_mask = MLXPLAT_CPLD_AGGR_FAN_MASK_DEF,
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.fan_reg_offset = MLXPLAT_CPLD_LPC_REG_FAN_ADRR,
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.fan_mask = MLXPLAT_CPLD_FAN_MASK,
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.fan_count = ARRAY_SIZE(mlxplat_mlxcpld_fan),
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.fan = mlxplat_mlxcpld_fan,
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};
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/* Platform hotplug MSN21xx system family data */
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static
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struct mlxcpld_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = {
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.top_aggr_offset = MLXPLAT_CPLD_LPC_REG_AGGR_ADRR,
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.top_aggr_mask = MLXPLAT_CPLD_AGGR_MASK_MSN21XX,
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.top_aggr_pwr_mask = MLXPLAT_CPLD_AGGR_MASK_MSN21XX,
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.pwr_reg_offset = MLXPLAT_CPLD_LPC_REG_PWR_ADRR,
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.pwr_mask = MLXPLAT_CPLD_PWR_MASK,
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.pwr_count = ARRAY_SIZE(mlxplat_mlxcpld_pwr),
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};
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static struct resource mlxplat_mlxcpld_resources[] = {
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[0] = DEFINE_RES_IRQ_NAMED(17, "mlxcpld-hotplug"),
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};
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struct platform_device *mlxplat_dev;
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struct mlxcpld_hotplug_platform_data *mlxplat_hotplug;
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static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mlxplat_mux_data); i++) {
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mlxplat_mux_data[i].values = mlxplat_default_channels[i];
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mlxplat_mux_data[i].n_values =
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ARRAY_SIZE(mlxplat_default_channels[i]);
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}
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mlxplat_hotplug = &mlxplat_mlxcpld_default_data;
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return 1;
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};
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static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mlxplat_mux_data); i++) {
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mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
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mlxplat_mux_data[i].n_values =
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ARRAY_SIZE(mlxplat_msn21xx_channels);
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}
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mlxplat_hotplug = &mlxplat_mlxcpld_msn21xx_data;
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return 1;
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};
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static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
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{
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.callback = mlxplat_dmi_default_matched,
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
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DMI_MATCH(DMI_PRODUCT_NAME, "MSN24"),
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},
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},
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{
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.callback = mlxplat_dmi_default_matched,
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
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DMI_MATCH(DMI_PRODUCT_NAME, "MSN27"),
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},
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},
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{
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.callback = mlxplat_dmi_default_matched,
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
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DMI_MATCH(DMI_PRODUCT_NAME, "MSB"),
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},
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},
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{
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.callback = mlxplat_dmi_default_matched,
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
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DMI_MATCH(DMI_PRODUCT_NAME, "MSX"),
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},
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},
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{
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.callback = mlxplat_dmi_msn21xx_matched,
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
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DMI_MATCH(DMI_PRODUCT_NAME, "MSN21"),
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},
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},
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{ }
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};
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static int __init mlxplat_init(void)
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{
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struct mlxplat_priv *priv;
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int i, err;
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if (!dmi_check_system(mlxplat_dmi_table))
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return -ENODEV;
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mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, -1,
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mlxplat_lpc_resources,
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ARRAY_SIZE(mlxplat_lpc_resources));
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if (IS_ERR(mlxplat_dev))
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return PTR_ERR(mlxplat_dev);
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priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv),
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GFP_KERNEL);
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if (!priv) {
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err = -ENOMEM;
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goto fail_alloc;
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}
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platform_set_drvdata(mlxplat_dev, priv);
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priv->pdev_i2c = platform_device_register_simple("i2c_mlxcpld", -1,
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NULL, 0);
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if (IS_ERR(priv->pdev_i2c)) {
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err = PTR_ERR(priv->pdev_i2c);
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goto fail_alloc;
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}
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for (i = 0; i < ARRAY_SIZE(mlxplat_mux_data); i++) {
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priv->pdev_mux[i] = platform_device_register_resndata(
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&mlxplat_dev->dev,
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"i2c-mux-reg", i, NULL,
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0, &mlxplat_mux_data[i],
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sizeof(mlxplat_mux_data[i]));
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if (IS_ERR(priv->pdev_mux[i])) {
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err = PTR_ERR(priv->pdev_mux[i]);
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goto fail_platform_mux_register;
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}
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}
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priv->pdev_hotplug = platform_device_register_resndata(
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&mlxplat_dev->dev, "mlxcpld-hotplug",
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PLATFORM_DEVID_NONE,
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mlxplat_mlxcpld_resources,
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ARRAY_SIZE(mlxplat_mlxcpld_resources),
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mlxplat_hotplug, sizeof(*mlxplat_hotplug));
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if (IS_ERR(priv->pdev_hotplug)) {
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err = PTR_ERR(priv->pdev_hotplug);
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goto fail_platform_mux_register;
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}
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return 0;
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fail_platform_mux_register:
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while (--i >= 0)
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platform_device_unregister(priv->pdev_mux[i]);
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platform_device_unregister(priv->pdev_i2c);
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fail_alloc:
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platform_device_unregister(mlxplat_dev);
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return err;
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}
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module_init(mlxplat_init);
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static void __exit mlxplat_exit(void)
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{
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struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);
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int i;
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platform_device_unregister(priv->pdev_hotplug);
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for (i = ARRAY_SIZE(mlxplat_mux_data) - 1; i >= 0 ; i--)
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platform_device_unregister(priv->pdev_mux[i]);
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platform_device_unregister(priv->pdev_i2c);
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platform_device_unregister(mlxplat_dev);
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}
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module_exit(mlxplat_exit);
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MODULE_AUTHOR("Vadim Pasternak (vadimp@mellanox.com)");
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MODULE_DESCRIPTION("Mellanox platform driver");
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MODULE_LICENSE("Dual BSD/GPL");
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MODULE_ALIAS("dmi:*:*Mellanox*:MSN24*:");
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MODULE_ALIAS("dmi:*:*Mellanox*:MSN27*:");
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MODULE_ALIAS("dmi:*:*Mellanox*:MSB*:");
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MODULE_ALIAS("dmi:*:*Mellanox*:MSX*:");
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MODULE_ALIAS("dmi:*:*Mellanox*:MSN21*:");
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