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2a22b7ae2f
Wangxun NICs support the connection with SFP to RJ45 module. In this case, PCS need to be configured in SGMII mode. According to chapter 6.11.1 "SGMII Auto-Negitiation" of DesignWare Cores Ethernet PCS (version 3.20a) and custom design manual, do the following configuration when the interface mode is SGMII. 1. program VR_MII_AN_CTRL bit(3) [TX_CONFIG] = 1b (PHY side SGMII) 2. program VR_MII_AN_CTRL bit(8) [MII_CTRL] = 1b (8-bit MII) 3. program VR_MII_DIG_CTRL1 bit(0) [PHY_MODE_CTRL] = 1b Also CL37 AN in backplane configurations need to be enabled because of the special hardware design. Another thing to note is that PMA needs to be reconfigured before each CL37 AN configuration for SGMII, otherwise AN will fail, although we don't know why. On this device, CL37_ANSGM_STS (bit[4:1] of VR_MII_AN_INTR_STS) indicates the status received from remote link during the auto-negotiation, and self-clear after the auto-negotiation is complete. Meanwhile, CL37_ANCMPLT_INTR will be set to 1, to indicate CL37 AN is complete. So add another way to get the state for CL37 SGMII. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
210 lines
7.2 KiB
C
210 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2015 - 2023 Beijing WangXun Technology Co., Ltd. */
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#include <linux/pcs/pcs-xpcs.h>
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#include <linux/mdio.h>
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#include "pcs-xpcs.h"
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/* VR_XS_PMA_MMD */
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#define TXGBE_PMA_MMD 0x8020
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#define TXGBE_TX_GENCTL1 0x11
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#define TXGBE_TX_GENCTL1_VBOOST_LVL GENMASK(10, 8)
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#define TXGBE_TX_GENCTL1_VBOOST_EN0 BIT(4)
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#define TXGBE_TX_GEN_CTL2 0x12
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#define TXGBE_TX_GEN_CTL2_TX0_WIDTH(v) FIELD_PREP(GENMASK(9, 8), v)
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#define TXGBE_TX_RATE_CTL 0x14
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#define TXGBE_TX_RATE_CTL_TX0_RATE(v) FIELD_PREP(GENMASK(2, 0), v)
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#define TXGBE_RX_GEN_CTL2 0x32
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#define TXGBE_RX_GEN_CTL2_RX0_WIDTH(v) FIELD_PREP(GENMASK(9, 8), v)
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#define TXGBE_RX_GEN_CTL3 0x33
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#define TXGBE_RX_GEN_CTL3_LOS_TRSHLD0 GENMASK(2, 0)
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#define TXGBE_RX_RATE_CTL 0x34
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#define TXGBE_RX_RATE_CTL_RX0_RATE(v) FIELD_PREP(GENMASK(1, 0), v)
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#define TXGBE_RX_EQ_ATTN_CTL 0x37
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#define TXGBE_RX_EQ_ATTN_LVL0 GENMASK(2, 0)
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#define TXGBE_RX_EQ_CTL0 0x38
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#define TXGBE_RX_EQ_CTL0_VGA1_GAIN(v) FIELD_PREP(GENMASK(15, 12), v)
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#define TXGBE_RX_EQ_CTL0_VGA2_GAIN(v) FIELD_PREP(GENMASK(11, 8), v)
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#define TXGBE_RX_EQ_CTL0_CTLE_POLE(v) FIELD_PREP(GENMASK(7, 5), v)
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#define TXGBE_RX_EQ_CTL0_CTLE_BOOST(v) FIELD_PREP(GENMASK(4, 0), v)
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#define TXGBE_RX_EQ_CTL4 0x3C
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#define TXGBE_RX_EQ_CTL4_CONT_OFF_CAN0 BIT(4)
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#define TXGBE_RX_EQ_CTL4_CONT_ADAPT0 BIT(0)
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#define TXGBE_AFE_DFE_ENABLE 0x3D
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#define TXGBE_DFE_EN_0 BIT(4)
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#define TXGBE_AFE_EN_0 BIT(0)
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#define TXGBE_DFE_TAP_CTL0 0x3E
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#define TXGBE_MPLLA_CTL0 0x51
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#define TXGBE_MPLLA_CTL2 0x53
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#define TXGBE_MPLLA_CTL2_DIV16P5_CLK_EN BIT(10)
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#define TXGBE_MPLLA_CTL2_DIV10_CLK_EN BIT(9)
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#define TXGBE_MPLLA_CTL3 0x57
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#define TXGBE_MISC_CTL0 0x70
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#define TXGBE_MISC_CTL0_PLL BIT(15)
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#define TXGBE_MISC_CTL0_CR_PARA_SEL BIT(14)
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#define TXGBE_MISC_CTL0_RX_VREF(v) FIELD_PREP(GENMASK(12, 8), v)
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#define TXGBE_VCO_CAL_LD0 0x72
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#define TXGBE_VCO_CAL_REF0 0x76
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static int txgbe_read_pma(struct dw_xpcs *xpcs, int reg)
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{
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return xpcs_read(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg);
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}
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static int txgbe_write_pma(struct dw_xpcs *xpcs, int reg, u16 val)
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{
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return xpcs_write(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg, val);
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}
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static void txgbe_pma_config_10gbaser(struct dw_xpcs *xpcs)
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{
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int val;
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txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL0, 0x21);
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txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL3, 0);
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val = txgbe_read_pma(xpcs, TXGBE_TX_GENCTL1);
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val = u16_replace_bits(val, 0x5, TXGBE_TX_GENCTL1_VBOOST_LVL);
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txgbe_write_pma(xpcs, TXGBE_TX_GENCTL1, val);
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txgbe_write_pma(xpcs, TXGBE_MISC_CTL0, TXGBE_MISC_CTL0_PLL |
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TXGBE_MISC_CTL0_CR_PARA_SEL | TXGBE_MISC_CTL0_RX_VREF(0xF));
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txgbe_write_pma(xpcs, TXGBE_VCO_CAL_LD0, 0x549);
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txgbe_write_pma(xpcs, TXGBE_VCO_CAL_REF0, 0x29);
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txgbe_write_pma(xpcs, TXGBE_TX_RATE_CTL, 0);
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txgbe_write_pma(xpcs, TXGBE_RX_RATE_CTL, 0);
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txgbe_write_pma(xpcs, TXGBE_TX_GEN_CTL2, TXGBE_TX_GEN_CTL2_TX0_WIDTH(3));
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txgbe_write_pma(xpcs, TXGBE_RX_GEN_CTL2, TXGBE_RX_GEN_CTL2_RX0_WIDTH(3));
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txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL2, TXGBE_MPLLA_CTL2_DIV16P5_CLK_EN |
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TXGBE_MPLLA_CTL2_DIV10_CLK_EN);
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txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL0, TXGBE_RX_EQ_CTL0_CTLE_POLE(2) |
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TXGBE_RX_EQ_CTL0_CTLE_BOOST(5));
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val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL);
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val &= ~TXGBE_RX_EQ_ATTN_LVL0;
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txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val);
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txgbe_write_pma(xpcs, TXGBE_DFE_TAP_CTL0, 0xBE);
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val = txgbe_read_pma(xpcs, TXGBE_AFE_DFE_ENABLE);
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val &= ~(TXGBE_DFE_EN_0 | TXGBE_AFE_EN_0);
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txgbe_write_pma(xpcs, TXGBE_AFE_DFE_ENABLE, val);
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val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_CTL4);
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val &= ~TXGBE_RX_EQ_CTL4_CONT_ADAPT0;
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txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL4, val);
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}
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static void txgbe_pma_config_1g(struct dw_xpcs *xpcs)
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{
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int val;
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val = txgbe_read_pma(xpcs, TXGBE_TX_GENCTL1);
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val = u16_replace_bits(val, 0x5, TXGBE_TX_GENCTL1_VBOOST_LVL);
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val &= ~TXGBE_TX_GENCTL1_VBOOST_EN0;
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txgbe_write_pma(xpcs, TXGBE_TX_GENCTL1, val);
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txgbe_write_pma(xpcs, TXGBE_MISC_CTL0, TXGBE_MISC_CTL0_PLL |
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TXGBE_MISC_CTL0_CR_PARA_SEL | TXGBE_MISC_CTL0_RX_VREF(0xF));
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txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL0, TXGBE_RX_EQ_CTL0_VGA1_GAIN(7) |
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TXGBE_RX_EQ_CTL0_VGA2_GAIN(7) | TXGBE_RX_EQ_CTL0_CTLE_BOOST(6));
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val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL);
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val &= ~TXGBE_RX_EQ_ATTN_LVL0;
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txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val);
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txgbe_write_pma(xpcs, TXGBE_DFE_TAP_CTL0, 0);
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val = txgbe_read_pma(xpcs, TXGBE_RX_GEN_CTL3);
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val = u16_replace_bits(val, 0x4, TXGBE_RX_GEN_CTL3_LOS_TRSHLD0);
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txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val);
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txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL0, 0x20);
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txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL3, 0x46);
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txgbe_write_pma(xpcs, TXGBE_VCO_CAL_LD0, 0x540);
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txgbe_write_pma(xpcs, TXGBE_VCO_CAL_REF0, 0x2A);
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txgbe_write_pma(xpcs, TXGBE_AFE_DFE_ENABLE, 0);
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txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL4, TXGBE_RX_EQ_CTL4_CONT_OFF_CAN0);
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txgbe_write_pma(xpcs, TXGBE_TX_RATE_CTL, TXGBE_TX_RATE_CTL_TX0_RATE(3));
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txgbe_write_pma(xpcs, TXGBE_RX_RATE_CTL, TXGBE_RX_RATE_CTL_RX0_RATE(3));
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txgbe_write_pma(xpcs, TXGBE_TX_GEN_CTL2, TXGBE_TX_GEN_CTL2_TX0_WIDTH(1));
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txgbe_write_pma(xpcs, TXGBE_RX_GEN_CTL2, TXGBE_RX_GEN_CTL2_RX0_WIDTH(1));
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txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL2, TXGBE_MPLLA_CTL2_DIV10_CLK_EN);
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}
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static int txgbe_pcs_poll_power_up(struct dw_xpcs *xpcs)
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{
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int val, ret;
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/* Wait xpcs power-up good */
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ret = read_poll_timeout(xpcs_read_vpcs, val,
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(val & DW_PSEQ_ST) == DW_PSEQ_ST_GOOD,
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10000, 1000000, false,
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xpcs, DW_VR_XS_PCS_DIG_STS);
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if (ret < 0)
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dev_err(&xpcs->mdiodev->dev, "xpcs power-up timeout\n");
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return ret;
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}
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static int txgbe_pma_init_done(struct dw_xpcs *xpcs)
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{
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int val, ret;
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xpcs_write_vpcs(xpcs, DW_VR_XS_PCS_DIG_CTRL1, DW_VR_RST | DW_EN_VSMMD1);
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/* wait pma initialization done */
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ret = read_poll_timeout(xpcs_read_vpcs, val, !(val & DW_VR_RST),
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100000, 10000000, false,
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xpcs, DW_VR_XS_PCS_DIG_CTRL1);
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if (ret < 0)
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dev_err(&xpcs->mdiodev->dev, "xpcs pma initialization timeout\n");
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return ret;
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}
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static bool txgbe_xpcs_mode_quirk(struct dw_xpcs *xpcs)
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{
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int ret;
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/* When txgbe do LAN reset, PCS will change to default 10GBASE-R mode */
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ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_CTRL2);
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ret &= MDIO_PCS_CTRL2_TYPE;
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if ((ret == MDIO_PCS_CTRL2_10GBR &&
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xpcs->interface != PHY_INTERFACE_MODE_10GBASER) ||
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xpcs->interface == PHY_INTERFACE_MODE_SGMII)
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return true;
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return false;
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}
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int txgbe_xpcs_switch_mode(struct dw_xpcs *xpcs, phy_interface_t interface)
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{
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int val, ret;
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switch (interface) {
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case PHY_INTERFACE_MODE_10GBASER:
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_1000BASEX:
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break;
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default:
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return 0;
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}
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if (xpcs->interface == interface && !txgbe_xpcs_mode_quirk(xpcs))
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return 0;
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xpcs->interface = interface;
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ret = txgbe_pcs_poll_power_up(xpcs);
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if (ret < 0)
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return ret;
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if (interface == PHY_INTERFACE_MODE_10GBASER) {
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xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL2, MDIO_PCS_CTRL2_10GBR);
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val = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1);
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val |= MDIO_CTRL1_SPEED10G;
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xpcs_write(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1, val);
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txgbe_pma_config_10gbaser(xpcs);
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} else {
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xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL2, MDIO_PCS_CTRL2_10GBX);
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xpcs_write(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1, 0);
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xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL1, 0);
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txgbe_pma_config_1g(xpcs);
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}
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return txgbe_pma_init_done(xpcs);
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}
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