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With the A80 SoC, Allwinner grouped and moved some subsystem specific clock controls to a separate address space, and possibly separate hardware block. One such subsystem is the display engine. The main clock control unit now only has 1 set of bus gate, dram gate, module clock, and reset control for the entire display subsystem. These feed into a secondary clock control unit, which has controls for each individual module of the display pipeline. This block is not documented in the user manual. Allwinner's kernel was used as the reference. Add support for the display engine clock controls found on the A80. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
81 lines
2.8 KiB
C
81 lines
2.8 KiB
C
/*
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* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_
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#define _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_
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#define CLK_FE0 0
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#define CLK_FE1 1
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#define CLK_FE2 2
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#define CLK_IEP_DEU0 3
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#define CLK_IEP_DEU1 4
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#define CLK_BE0 5
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#define CLK_BE1 6
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#define CLK_BE2 7
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#define CLK_IEP_DRC0 8
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#define CLK_IEP_DRC1 9
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#define CLK_MERGE 10
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#define CLK_DRAM_FE0 11
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#define CLK_DRAM_FE1 12
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#define CLK_DRAM_FE2 13
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#define CLK_DRAM_DEU0 14
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#define CLK_DRAM_DEU1 15
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#define CLK_DRAM_BE0 16
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#define CLK_DRAM_BE1 17
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#define CLK_DRAM_BE2 18
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#define CLK_DRAM_DRC0 19
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#define CLK_DRAM_DRC1 20
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#define CLK_BUS_FE0 21
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#define CLK_BUS_FE1 22
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#define CLK_BUS_FE2 23
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#define CLK_BUS_DEU0 24
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#define CLK_BUS_DEU1 25
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#define CLK_BUS_BE0 26
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#define CLK_BUS_BE1 27
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#define CLK_BUS_BE2 28
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#define CLK_BUS_DRC0 29
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#define CLK_BUS_DRC1 30
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#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ */
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