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Add binding documentation for Ingenic SoC interrupt controllers. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Kumar Gala <galak@codeaurora.org> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10134/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
29 lines
827 B
Plaintext
29 lines
827 B
Plaintext
Ingenic SoC Interrupt Controller
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Required properties:
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- compatible : should be "ingenic,<socname>-intc". Valid strings are:
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ingenic,jz4740-intc
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ingenic,jz4770-intc
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ingenic,jz4775-intc
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ingenic,jz4780-intc
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- reg : Specifies base physical address and size of the registers.
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The value shall be 1.
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- interrupt-parent : phandle of the CPU interrupt controller.
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- interrupts : Specifies the CPU interrupt the controller is connected to.
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Example:
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intc: interrupt-controller@10001000 {
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compatible = "ingenic,jz4740-intc";
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reg = <0x10001000 0x14>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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