linux/include/dt-bindings/clock/sun4i-a10-pll2.h
Maxime Ripard 460d0d4448 clk: sunxi: Add a driver for the PLL2
The PLL2 on the A10 and later SoCs is the clock used for all the audio
related operations.

This clock has a somewhat complex output tree, with three outputs (2X, 4X
and 8X) with a fixed divider from the base clock, and an output (1X) with a
post divider.

However, we can simplify things since the 1X divider can be fixed, and we
end up by having a base clock not exposed to any device (or at least
directly, since the 4X output doesn't have any divider), and 4 fixed
divider clocks that will be exposed.

This clock seems to have been introduced, at least in this form, in the
revision B of the A10, but we don't have any information on the clock used
on the revision A.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
2015-10-21 21:51:27 +02:00

54 lines
2.2 KiB
C

/*
* Copyright 2015 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
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* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
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#ifndef __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_
#define __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_
#define SUN4I_A10_PLL2_1X 0
#define SUN4I_A10_PLL2_2X 1
#define SUN4I_A10_PLL2_4X 2
#define SUN4I_A10_PLL2_8X 3
#endif /* __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ */