Dave Martin 41040cf7c5 arm64/sve: Fix missing SVE/FPSIMD endianness conversions ... The in-memory representation of SVE and FPSIMD registers is different: the FPSIMD V-registers are stored as single 128-bit host-endian values, whereas SVE registers are stored in an endianness-invariant byte order. This means that the two representations differ when running on a big-endian host. But we blindly copy data from one representation to another when converting between the two, resulting in the register contents being unintentionally byteswapped in certain situations. Currently this can be triggered by the first SVE instruction after a syscall, for example (though the potential trigger points may vary in future). So, fix the conversion functions fpsimd_to_sve(), sve_to_fpsimd() and sve_sync_from_fpsimd_zeropad() to swab where appropriate. There is no common swahl128() or swab128() that we could use here. Maybe it would be worth making this generic, but for now add a simple local hack. Since the byte order differences are exposed in ABI, also clarify the documentation. Cc: Alex Bennée <alex.bennee@linaro.org> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Alan Hayward <alan.hayward@arm.com> Cc: Julien Grall <julien.grall@arm.com> Fixes: bc0ee47603 ("arm64/sve: Core task context handling") Fixes: 8cd969d28f ("arm64/sve: Signal handling support") Fixes: 43d4da2c45 ("arm64/sve: ptrace and ELF coredump support") Signed-off-by: Dave Martin <Dave.Martin@arm.com> [will: Fix typos in comments and docs spotted by Julien] Signed-off-by: Will Deacon <will.deacon@arm.com>		2019-06-13 10:07:19 +01:00
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asm	arm64: tlbflush: Ensure start/end of address range are aligned to stride	2019-06-12 16:19:45 +01:00
uapi/asm	arm64/sve: Fix missing SVE/FPSIMD endianness conversions	2019-06-13 10:07:19 +01:00