mirror of
https://github.com/torvalds/linux.git
synced 2024-11-17 17:41:44 +00:00
1394f03221
This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
96 lines
2.4 KiB
C
96 lines
2.4 KiB
C
/************************************************************************
|
|
*
|
|
* macros.h
|
|
*
|
|
* (c) Copyright 2001-2003 Analog Devices, Inc. All rights reserved.
|
|
*
|
|
************************************************************************/
|
|
|
|
/* Defines various assembly macros. */
|
|
|
|
#ifndef _MACROS_H
|
|
#define _MACROS_H
|
|
|
|
#define LO(con32) ((con32) & 0xFFFF)
|
|
#define lo(con32) ((con32) & 0xFFFF)
|
|
#define HI(con32) (((con32) >> 16) & 0xFFFF)
|
|
#define hi(con32) (((con32) >> 16) & 0xFFFF)
|
|
|
|
/*
|
|
* Set the corresponding bits in a System Register (SR);
|
|
* All bits set in "mask" will be set in the system register
|
|
* specified by "sys_reg" bitset_SR(sys_reg, mask), where
|
|
* sys_reg is the system register and mask are the bits to be set.
|
|
*/
|
|
#define bitset_SR(sys_reg, mask)\
|
|
[--SP] = (R7:6);\
|
|
r7 = sys_reg;\
|
|
r6.l = (mask) & 0xffff;\
|
|
r6.h = (mask) >> 16;\
|
|
r7 = r7 | r6;\
|
|
sys_reg = r7;\
|
|
csync;\
|
|
(R7:6) = [SP++]
|
|
|
|
/*
|
|
* Clear the corresponding bits in a System Register (SR);
|
|
* All bits set in "mask" will be cleared in the SR
|
|
* specified by "sys_reg" bitclr_SR(sys_reg, mask), where
|
|
* sys_reg is the SR and mask are the bits to be cleared.
|
|
*/
|
|
#define bitclr_SR(sys_reg, mask)\
|
|
[--SP] = (R7:6);\
|
|
r7 = sys_reg;\
|
|
r7 =~ r7;\
|
|
r6.l = (mask) & 0xffff;\
|
|
r6.h = (mask) >> 16;\
|
|
r7 = r7 | r6;\
|
|
r7 =~ r7;\
|
|
sys_reg = r7;\
|
|
csync;\
|
|
(R7:6) = [SP++]
|
|
|
|
/*
|
|
* Set the corresponding bits in a Memory Mapped Register (MMR);
|
|
* All bits set in "mask" will be set in the MMR specified by "mmr_reg"
|
|
* bitset_MMR(mmr_reg, mask), where mmr_reg is the MMR and mask are
|
|
* the bits to be set.
|
|
*/
|
|
#define bitset_MMR(mmr_reg, mask)\
|
|
[--SP] = (R7:6);\
|
|
[--SP] = P5;\
|
|
p5.l = mmr_reg & 0xffff;\
|
|
p5.h = mmr_reg >> 16;\
|
|
r7 = [p5];\
|
|
r6.l = (mask) & 0xffff;\
|
|
r6.h = (mask) >> 16;\
|
|
r7 = r7 | r6;\
|
|
[p5] = r7;\
|
|
csync;\
|
|
p5 = [SP++];\
|
|
(R7:6) = [SP++]
|
|
|
|
/*
|
|
* Clear the corresponding bits in a Memory Mapped Register (MMR);
|
|
* All bits set in "mask" will be cleared in the MMR specified by "mmr_reg"
|
|
* bitclr_MMRreg(mmr_reg, mask), where sys_reg is the MMR and mask are
|
|
* the bits to be cleared.
|
|
*/
|
|
#define bitclr_MMR(mmr_reg, mask)\
|
|
[--SP] = (R7:6);\
|
|
[--SP] = P5;\
|
|
p5.l = mmr_reg & 0xffff;\
|
|
p5.h = mmr_reg >> 16;\
|
|
r7 = [p5];\
|
|
r7 =~ r7;\
|
|
r6.l = (mask) & 0xffff;\
|
|
r6.h = (mask) >> 16;\
|
|
r7 = r7 | r6;\
|
|
r7 =~ r7;\
|
|
[p5] = r7;\
|
|
csync;\
|
|
p5 = [SP++];\
|
|
(R7:6) = [SP++]
|
|
|
|
#endif /* _MACROS_H */
|