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c56e7a4c3e
Space reserved for PKMap should span from PKMAP_BASE to FIXADDR_START. For large page sizes this is not the case as eg. for 64k pages the range currently defined is from 0xfe000000 to 0x102000000(!!) which obviously isn't right. Remove the hardcoded location and set the BASE address as an offset from FIXADDR_START. Since all PKMAP ptes have to be placed in a contiguous memory, ensure that this is the case by placing them all in a single page. This is achieved by aligning the end address to pkmap pages count pages. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/15950/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
226 lines
7.2 KiB
C
226 lines
7.2 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
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* Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_PGTABLE_32_H
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#define _ASM_PGTABLE_32_H
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#include <asm/addrspace.h>
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#include <asm/page.h>
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#include <linux/linkage.h>
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#include <asm/cachectl.h>
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#include <asm/fixmap.h>
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#define __ARCH_USE_5LEVEL_HACK
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#include <asm-generic/pgtable-nopmd.h>
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#ifdef CONFIG_HIGHMEM
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#include <asm/highmem.h>
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#endif
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extern int temp_tlb_entry;
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/*
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* - add_temporary_entry() add a temporary TLB entry. We use TLB entries
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* starting at the top and working down. This is for populating the
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* TLB before trap_init() puts the TLB miss handler in place. It
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* should be used only for entries matching the actual page tables,
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* to prevent inconsistencies.
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*/
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extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
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unsigned long entryhi, unsigned long pagemask);
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/*
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* Basically we have the same two-level (which is the logical three level
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* Linux page table layout folded) page tables as the i386. Some day
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* when we have proper page coloring support we can have a 1% quicker
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* tlb refill handling mechanism, but for now it is a bit slower but
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* works even with the cache aliasing problem the R4k and above have.
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*/
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/* PGDIR_SHIFT determines what a third-level page table entry can map */
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#define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* Entries per page directory level: we use two-level, so
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* we don't really have any PUD/PMD directory physically.
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*/
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#define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
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#define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
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#define PUD_ORDER aieeee_attempt_to_allocate_pud
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#define PMD_ORDER 1
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#define PTE_ORDER 0
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#define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2)
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#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
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#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
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#define FIRST_USER_ADDRESS 0UL
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#define VMALLOC_START MAP_BASE
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#define PKMAP_END ((FIXADDR_START) & ~((LAST_PKMAP << PAGE_SHIFT)-1))
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#define PKMAP_BASE (PKMAP_END - PAGE_SIZE * LAST_PKMAP)
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#ifdef CONFIG_HIGHMEM
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# define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
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#else
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# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
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#endif
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
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#else
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
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#endif
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
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extern void load_pgd(unsigned long pg_dir);
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extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
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/*
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* Empty pgd/pmd entries point to the invalid_pte_table.
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*/
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static inline int pmd_none(pmd_t pmd)
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{
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return pmd_val(pmd) == (unsigned long) invalid_pte_table;
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}
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#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
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static inline int pmd_present(pmd_t pmd)
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{
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return pmd_val(pmd) != (unsigned long) invalid_pte_table;
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}
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static inline void pmd_clear(pmd_t *pmdp)
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{
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pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
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}
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#if defined(CONFIG_XPA)
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#define pte_pfn(x) (((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT))
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static inline pte_t
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pfn_pte(unsigned long pfn, pgprot_t prot)
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{
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pte_t pte;
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pte.pte_low = (pfn >> _PAGE_PRESENT_SHIFT) |
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(pgprot_val(prot) & ~_PFNX_MASK);
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pte.pte_high = (pfn << _PFN_SHIFT) |
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(pgprot_val(prot) & ~_PFN_MASK);
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return pte;
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}
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#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
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#define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
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static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
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{
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pte_t pte;
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pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
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pte.pte_low = pgprot_val(prot);
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return pte;
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}
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#else
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#ifdef CONFIG_CPU_VR41XX
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#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
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#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
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#else
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#define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT))
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#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
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#endif
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#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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#define __pgd_offset(address) pgd_index(address)
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#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
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#define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
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/* to find an entry in a kernel page-table-directory */
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#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
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/* to find an entry in a page-table-directory */
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#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
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/* Find an entry in the third-level page table.. */
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#define __pte_offset(address) \
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(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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#define pte_offset(dir, address) \
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((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
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#define pte_offset_kernel(dir, address) \
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((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
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#define pte_offset_map(dir, address) \
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((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
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#define pte_unmap(pte) ((void)(pte))
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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/* Swap entries must have VALID bit cleared. */
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#define __swp_type(x) (((x).val >> 10) & 0x1f)
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#define __swp_offset(x) ((x).val >> 15)
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#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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#else
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#if defined(CONFIG_XPA)
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/* Swap entries must have VALID and GLOBAL bits cleared. */
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#define __swp_type(x) (((x).val >> 4) & 0x1f)
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#define __swp_offset(x) ((x).val >> 9)
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#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 4) | ((offset) << 9) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
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#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
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#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
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/* Swap entries must have VALID and GLOBAL bits cleared. */
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#define __swp_type(x) (((x).val >> 2) & 0x1f)
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#define __swp_offset(x) ((x).val >> 7)
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#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 7) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
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#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
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#else
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/*
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* Constraints:
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* _PAGE_PRESENT at bit 0
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* _PAGE_MODIFIED at bit 4
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* _PAGE_GLOBAL at bit 6
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* _PAGE_VALID at bit 7
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*/
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#define __swp_type(x) (((x).val >> 8) & 0x1f)
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#define __swp_offset(x) ((x).val >> 13)
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#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
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#endif /* defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) */
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#endif /* _ASM_PGTABLE_32_H */
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