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201ddc0577
A proper clock driver for ralink SoCs has been added. This driver is also a reset provider for the SoC. Hence there is no need to have reset related code in 'arch/mips/ralink' folder anymore. The only code that remains is the one related with mips_reboot_setup where a PCI reset is performed. We maintain this because I cannot test old ralink board with PCI to be sure all works if we remove also this code. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
44 lines
878 B
C
44 lines
878 B
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2013 John Crispin <john@phrozen.org>
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*/
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#include <linux/pm.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/delay.h>
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#include <asm/reboot.h>
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#include <asm/mach-ralink/ralink_regs.h>
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/* Reset Control */
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#define SYSC_REG_RESET_CTRL 0x034
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#define RSTCTL_RESET_PCI BIT(26)
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#define RSTCTL_RESET_SYSTEM BIT(0)
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static void ralink_restart(char *command)
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{
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if (IS_ENABLED(CONFIG_PCI)) {
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rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL);
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mdelay(50);
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}
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local_irq_disable();
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rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
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unreachable();
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}
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static int __init mips_reboot_setup(void)
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{
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_machine_restart = ralink_restart;
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return 0;
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}
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arch_initcall(mips_reboot_setup);
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