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cd2567b685
Performing vma lookups without taking the mm->mmap_sem is asking for trouble. While doing the search, the vma in question can be modified or even removed before returning to the caller. Take the lock (shared) in order to avoid races while iterating through the vmacache and/or rbtree. In addition, this guarantees that the address space will remain intact during the CPU flushing. Signed-off-by: Davidlohr Bueso <davidlohr@hp.com> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
573 lines
13 KiB
C
573 lines
13 KiB
C
/*
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* linux/arch/m68k/kernel/sys_m68k.c
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*
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* This file contains various random system calls that
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* have a non-standard calling sequence on the Linux/m68k
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* platform.
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*/
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#include <linux/capability.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/fs.h>
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#include <linux/smp.h>
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#include <linux/sem.h>
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#include <linux/msg.h>
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#include <linux/shm.h>
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#include <linux/stat.h>
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#include <linux/syscalls.h>
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#include <linux/mman.h>
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#include <linux/file.h>
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#include <linux/ipc.h>
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#include <asm/setup.h>
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#include <asm/uaccess.h>
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#include <asm/cachectl.h>
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#include <asm/traps.h>
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#include <asm/page.h>
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#include <asm/unistd.h>
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#include <asm/cacheflush.h>
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#ifdef CONFIG_MMU
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#include <asm/tlb.h>
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asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address,
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unsigned long error_code);
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asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
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unsigned long prot, unsigned long flags,
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unsigned long fd, unsigned long pgoff)
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{
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/*
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* This is wrong for sun3 - there PAGE_SIZE is 8Kb,
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* so we need to shift the argument down by 1; m68k mmap64(3)
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* (in libc) expects the last argument of mmap2 in 4Kb units.
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*/
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return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
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}
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/* Convert virtual (user) address VADDR to physical address PADDR */
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#define virt_to_phys_040(vaddr) \
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({ \
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unsigned long _mmusr, _paddr; \
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\
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__asm__ __volatile__ (".chip 68040\n\t" \
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"ptestr (%1)\n\t" \
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"movec %%mmusr,%0\n\t" \
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".chip 68k" \
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: "=r" (_mmusr) \
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: "a" (vaddr)); \
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_paddr = (_mmusr & MMU_R_040) ? (_mmusr & PAGE_MASK) : 0; \
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_paddr; \
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})
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static inline int
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cache_flush_040 (unsigned long addr, int scope, int cache, unsigned long len)
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{
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unsigned long paddr, i;
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switch (scope)
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{
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case FLUSH_SCOPE_ALL:
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switch (cache)
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{
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case FLUSH_CACHE_DATA:
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/* This nop is needed for some broken versions of the 68040. */
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__asm__ __volatile__ ("nop\n\t"
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".chip 68040\n\t"
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"cpusha %dc\n\t"
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".chip 68k");
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break;
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case FLUSH_CACHE_INSN:
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__asm__ __volatile__ ("nop\n\t"
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".chip 68040\n\t"
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"cpusha %ic\n\t"
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".chip 68k");
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break;
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default:
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case FLUSH_CACHE_BOTH:
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__asm__ __volatile__ ("nop\n\t"
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".chip 68040\n\t"
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"cpusha %bc\n\t"
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".chip 68k");
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break;
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}
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break;
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case FLUSH_SCOPE_LINE:
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/* Find the physical address of the first mapped page in the
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address range. */
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if ((paddr = virt_to_phys_040(addr))) {
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paddr += addr & ~(PAGE_MASK | 15);
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len = (len + (addr & 15) + 15) >> 4;
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} else {
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unsigned long tmp = PAGE_SIZE - (addr & ~PAGE_MASK);
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if (len <= tmp)
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return 0;
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addr += tmp;
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len -= tmp;
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tmp = PAGE_SIZE;
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for (;;)
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{
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if ((paddr = virt_to_phys_040(addr)))
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break;
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if (len <= tmp)
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return 0;
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addr += tmp;
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len -= tmp;
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}
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len = (len + 15) >> 4;
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}
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i = (PAGE_SIZE - (paddr & ~PAGE_MASK)) >> 4;
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while (len--)
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{
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switch (cache)
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{
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case FLUSH_CACHE_DATA:
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__asm__ __volatile__ ("nop\n\t"
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".chip 68040\n\t"
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"cpushl %%dc,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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break;
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case FLUSH_CACHE_INSN:
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__asm__ __volatile__ ("nop\n\t"
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".chip 68040\n\t"
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"cpushl %%ic,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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break;
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default:
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case FLUSH_CACHE_BOTH:
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__asm__ __volatile__ ("nop\n\t"
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".chip 68040\n\t"
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"cpushl %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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break;
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}
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if (!--i && len)
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{
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/*
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* No need to page align here since it is done by
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* virt_to_phys_040().
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*/
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addr += PAGE_SIZE;
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i = PAGE_SIZE / 16;
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/* Recompute physical address when crossing a page
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boundary. */
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for (;;)
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{
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if ((paddr = virt_to_phys_040(addr)))
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break;
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if (len <= i)
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return 0;
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len -= i;
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addr += PAGE_SIZE;
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}
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}
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else
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paddr += 16;
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}
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break;
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default:
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case FLUSH_SCOPE_PAGE:
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len += (addr & ~PAGE_MASK) + (PAGE_SIZE - 1);
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for (len >>= PAGE_SHIFT; len--; addr += PAGE_SIZE)
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{
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if (!(paddr = virt_to_phys_040(addr)))
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continue;
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switch (cache)
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{
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case FLUSH_CACHE_DATA:
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__asm__ __volatile__ ("nop\n\t"
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".chip 68040\n\t"
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"cpushp %%dc,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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break;
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case FLUSH_CACHE_INSN:
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__asm__ __volatile__ ("nop\n\t"
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".chip 68040\n\t"
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"cpushp %%ic,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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break;
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default:
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case FLUSH_CACHE_BOTH:
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__asm__ __volatile__ ("nop\n\t"
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".chip 68040\n\t"
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"cpushp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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break;
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}
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}
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break;
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}
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return 0;
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}
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#define virt_to_phys_060(vaddr) \
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({ \
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unsigned long paddr; \
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__asm__ __volatile__ (".chip 68060\n\t" \
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"plpar (%0)\n\t" \
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".chip 68k" \
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: "=a" (paddr) \
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: "0" (vaddr)); \
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(paddr); /* XXX */ \
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})
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static inline int
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cache_flush_060 (unsigned long addr, int scope, int cache, unsigned long len)
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{
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unsigned long paddr, i;
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/*
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* 68060 manual says:
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* cpush %dc : flush DC, remains valid (with our %cacr setup)
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* cpush %ic : invalidate IC
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* cpush %bc : flush DC + invalidate IC
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*/
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switch (scope)
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{
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case FLUSH_SCOPE_ALL:
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switch (cache)
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{
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case FLUSH_CACHE_DATA:
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__asm__ __volatile__ (".chip 68060\n\t"
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"cpusha %dc\n\t"
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".chip 68k");
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break;
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case FLUSH_CACHE_INSN:
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__asm__ __volatile__ (".chip 68060\n\t"
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"cpusha %ic\n\t"
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".chip 68k");
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break;
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default:
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case FLUSH_CACHE_BOTH:
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__asm__ __volatile__ (".chip 68060\n\t"
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"cpusha %bc\n\t"
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".chip 68k");
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break;
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}
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break;
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case FLUSH_SCOPE_LINE:
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/* Find the physical address of the first mapped page in the
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address range. */
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len += addr & 15;
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addr &= -16;
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if (!(paddr = virt_to_phys_060(addr))) {
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unsigned long tmp = PAGE_SIZE - (addr & ~PAGE_MASK);
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if (len <= tmp)
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return 0;
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addr += tmp;
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len -= tmp;
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tmp = PAGE_SIZE;
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for (;;)
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{
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if ((paddr = virt_to_phys_060(addr)))
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break;
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if (len <= tmp)
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return 0;
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addr += tmp;
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len -= tmp;
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}
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}
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len = (len + 15) >> 4;
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i = (PAGE_SIZE - (paddr & ~PAGE_MASK)) >> 4;
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while (len--)
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{
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switch (cache)
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{
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case FLUSH_CACHE_DATA:
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__asm__ __volatile__ (".chip 68060\n\t"
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"cpushl %%dc,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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break;
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case FLUSH_CACHE_INSN:
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__asm__ __volatile__ (".chip 68060\n\t"
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"cpushl %%ic,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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break;
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default:
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case FLUSH_CACHE_BOTH:
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__asm__ __volatile__ (".chip 68060\n\t"
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"cpushl %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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break;
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}
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if (!--i && len)
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{
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/*
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* We just want to jump to the first cache line
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* in the next page.
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*/
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addr += PAGE_SIZE;
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addr &= PAGE_MASK;
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i = PAGE_SIZE / 16;
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/* Recompute physical address when crossing a page
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boundary. */
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for (;;)
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{
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if ((paddr = virt_to_phys_060(addr)))
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break;
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if (len <= i)
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return 0;
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len -= i;
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addr += PAGE_SIZE;
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}
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}
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else
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paddr += 16;
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}
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break;
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default:
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case FLUSH_SCOPE_PAGE:
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len += (addr & ~PAGE_MASK) + (PAGE_SIZE - 1);
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addr &= PAGE_MASK; /* Workaround for bug in some
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revisions of the 68060 */
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for (len >>= PAGE_SHIFT; len--; addr += PAGE_SIZE)
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{
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if (!(paddr = virt_to_phys_060(addr)))
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continue;
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switch (cache)
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{
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case FLUSH_CACHE_DATA:
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__asm__ __volatile__ (".chip 68060\n\t"
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"cpushp %%dc,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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break;
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case FLUSH_CACHE_INSN:
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__asm__ __volatile__ (".chip 68060\n\t"
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"cpushp %%ic,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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break;
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default:
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case FLUSH_CACHE_BOTH:
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__asm__ __volatile__ (".chip 68060\n\t"
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"cpushp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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break;
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}
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}
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break;
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}
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return 0;
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}
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/* sys_cacheflush -- flush (part of) the processor cache. */
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asmlinkage int
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sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len)
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{
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int ret = -EINVAL;
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if (scope < FLUSH_SCOPE_LINE || scope > FLUSH_SCOPE_ALL ||
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cache & ~FLUSH_CACHE_BOTH)
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goto out;
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if (scope == FLUSH_SCOPE_ALL) {
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/* Only the superuser may explicitly flush the whole cache. */
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ret = -EPERM;
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if (!capable(CAP_SYS_ADMIN))
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goto out;
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} else {
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struct vm_area_struct *vma;
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/* Check for overflow. */
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if (addr + len < addr)
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goto out;
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/*
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* Verify that the specified address region actually belongs
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* to this process.
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*/
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ret = -EINVAL;
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down_read(¤t->mm->mmap_sem);
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vma = find_vma(current->mm, addr);
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if (!vma || addr < vma->vm_start || addr + len > vma->vm_end)
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goto out_unlock;
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}
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if (CPU_IS_020_OR_030) {
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if (scope == FLUSH_SCOPE_LINE && len < 256) {
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unsigned long cacr;
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__asm__ ("movec %%cacr, %0" : "=r" (cacr));
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if (cache & FLUSH_CACHE_INSN)
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cacr |= 4;
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if (cache & FLUSH_CACHE_DATA)
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cacr |= 0x400;
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len >>= 2;
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while (len--) {
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__asm__ __volatile__ ("movec %1, %%caar\n\t"
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"movec %0, %%cacr"
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: /* no outputs */
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: "r" (cacr), "r" (addr));
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addr += 4;
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}
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} else {
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/* Flush the whole cache, even if page granularity requested. */
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unsigned long cacr;
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__asm__ ("movec %%cacr, %0" : "=r" (cacr));
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if (cache & FLUSH_CACHE_INSN)
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cacr |= 8;
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if (cache & FLUSH_CACHE_DATA)
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cacr |= 0x800;
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__asm__ __volatile__ ("movec %0, %%cacr" : : "r" (cacr));
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}
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ret = 0;
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goto out_unlock;
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} else {
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/*
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* 040 or 060: don't blindly trust 'scope', someone could
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* try to flush a few megs of memory.
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*/
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if (len>=3*PAGE_SIZE && scope<FLUSH_SCOPE_PAGE)
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scope=FLUSH_SCOPE_PAGE;
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if (len>=10*PAGE_SIZE && scope<FLUSH_SCOPE_ALL)
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scope=FLUSH_SCOPE_ALL;
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if (CPU_IS_040) {
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ret = cache_flush_040 (addr, scope, cache, len);
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} else if (CPU_IS_060) {
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ret = cache_flush_060 (addr, scope, cache, len);
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}
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}
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out_unlock:
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up_read(¤t->mm->mmap_sem);
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out:
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return ret;
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}
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/* This syscall gets its arguments in A0 (mem), D2 (oldval) and
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D1 (newval). */
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asmlinkage int
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sys_atomic_cmpxchg_32(unsigned long newval, int oldval, int d3, int d4, int d5,
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unsigned long __user * mem)
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{
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/* This was borrowed from ARM's implementation. */
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for (;;) {
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struct mm_struct *mm = current->mm;
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pgd_t *pgd;
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pmd_t *pmd;
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pte_t *pte;
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spinlock_t *ptl;
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unsigned long mem_value;
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down_read(&mm->mmap_sem);
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pgd = pgd_offset(mm, (unsigned long)mem);
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if (!pgd_present(*pgd))
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goto bad_access;
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pmd = pmd_offset(pgd, (unsigned long)mem);
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if (!pmd_present(*pmd))
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goto bad_access;
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pte = pte_offset_map_lock(mm, pmd, (unsigned long)mem, &ptl);
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if (!pte_present(*pte) || !pte_dirty(*pte)
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|| !pte_write(*pte)) {
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pte_unmap_unlock(pte, ptl);
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goto bad_access;
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}
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/*
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* No need to check for EFAULT; we know that the page is
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* present and writable.
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*/
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__get_user(mem_value, mem);
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if (mem_value == oldval)
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__put_user(newval, mem);
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pte_unmap_unlock(pte, ptl);
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up_read(&mm->mmap_sem);
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return mem_value;
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bad_access:
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up_read(&mm->mmap_sem);
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/* This is not necessarily a bad access, we can get here if
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a memory we're trying to write to should be copied-on-write.
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Make the kernel do the necessary page stuff, then re-iterate.
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Simulate a write access fault to do that. */
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{
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/* The first argument of the function corresponds to
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D1, which is the first field of struct pt_regs. */
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struct pt_regs *fp = (struct pt_regs *)&newval;
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/* '3' is an RMW flag. */
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if (do_page_fault(fp, (unsigned long)mem, 3))
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/* If the do_page_fault() failed, we don't
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have anything meaningful to return.
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There should be a SIGSEGV pending for
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the process. */
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return 0xdeadbeef;
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}
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}
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}
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#else
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/* sys_cacheflush -- flush (part of) the processor cache. */
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asmlinkage int
|
|
sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len)
|
|
{
|
|
flush_cache_all();
|
|
return 0;
|
|
}
|
|
|
|
/* This syscall gets its arguments in A0 (mem), D2 (oldval) and
|
|
D1 (newval). */
|
|
asmlinkage int
|
|
sys_atomic_cmpxchg_32(unsigned long newval, int oldval, int d3, int d4, int d5,
|
|
unsigned long __user * mem)
|
|
{
|
|
struct mm_struct *mm = current->mm;
|
|
unsigned long mem_value;
|
|
|
|
down_read(&mm->mmap_sem);
|
|
|
|
mem_value = *mem;
|
|
if (mem_value == oldval)
|
|
*mem = newval;
|
|
|
|
up_read(&mm->mmap_sem);
|
|
return mem_value;
|
|
}
|
|
|
|
#endif /* CONFIG_MMU */
|
|
|
|
asmlinkage int sys_getpagesize(void)
|
|
{
|
|
return PAGE_SIZE;
|
|
}
|
|
|
|
asmlinkage unsigned long sys_get_thread_area(void)
|
|
{
|
|
return current_thread_info()->tp_value;
|
|
}
|
|
|
|
asmlinkage int sys_set_thread_area(unsigned long tp)
|
|
{
|
|
current_thread_info()->tp_value = tp;
|
|
return 0;
|
|
}
|
|
|
|
asmlinkage int sys_atomic_barrier(void)
|
|
{
|
|
/* no code needed for uniprocs */
|
|
return 0;
|
|
}
|