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335 lines
8.3 KiB
ArmAsm
335 lines
8.3 KiB
ArmAsm
/* sun4v_ivec.S: Sun4v interrupt vector handling.
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*
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* Copyright (C) 2006 <davem@davemloft.net>
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*/
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#include <asm/cpudata.h>
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#include <asm/intr_queue.h>
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.text
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.align 32
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sun4v_cpu_mondo:
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/* Head offset in %g2, tail offset in %g4.
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* If they are the same, no work.
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*/
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mov INTRQ_CPU_MONDO_HEAD, %g2
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ldxa [%g2] ASI_QUEUE, %g2
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mov INTRQ_CPU_MONDO_TAIL, %g4
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ldxa [%g4] ASI_QUEUE, %g4
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cmp %g2, %g4
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be,pn %xcc, sun4v_cpu_mondo_queue_empty
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nop
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/* Get &trap_block[smp_processor_id()] into %g3. */
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ldxa [%g0] ASI_SCRATCHPAD, %g3
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sub %g3, TRAP_PER_CPU_FAULT_INFO, %g3
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/* Get CPU mondo queue base phys address into %g7. */
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ldx [%g3 + TRAP_PER_CPU_CPU_MONDO_PA], %g7
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/* Now get the cross-call arguments and handler PC, same
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* layout as sun4u:
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*
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* 1st 64-bit word: low half is 32-bit PC, put into %g3 and jmpl to it
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* high half is context arg to MMU flushes, into %g5
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* 2nd 64-bit word: 64-bit arg, load into %g1
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* 3rd 64-bit word: 64-bit arg, load into %g7
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*/
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ldxa [%g7 + %g2] ASI_PHYS_USE_EC, %g3
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add %g2, 0x8, %g2
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srlx %g3, 32, %g5
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ldxa [%g7 + %g2] ASI_PHYS_USE_EC, %g1
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add %g2, 0x8, %g2
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srl %g3, 0, %g3
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ldxa [%g7 + %g2] ASI_PHYS_USE_EC, %g7
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add %g2, 0x40 - 0x8 - 0x8, %g2
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/* Update queue head pointer. */
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sethi %hi(8192 - 1), %g4
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or %g4, %lo(8192 - 1), %g4
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and %g2, %g4, %g2
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mov INTRQ_CPU_MONDO_HEAD, %g4
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stxa %g2, [%g4] ASI_QUEUE
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membar #Sync
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jmpl %g3, %g0
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nop
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sun4v_cpu_mondo_queue_empty:
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retry
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sun4v_dev_mondo:
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/* Head offset in %g2, tail offset in %g4. */
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mov INTRQ_DEVICE_MONDO_HEAD, %g2
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ldxa [%g2] ASI_QUEUE, %g2
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mov INTRQ_DEVICE_MONDO_TAIL, %g4
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ldxa [%g4] ASI_QUEUE, %g4
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cmp %g2, %g4
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be,pn %xcc, sun4v_dev_mondo_queue_empty
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nop
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/* Get &trap_block[smp_processor_id()] into %g3. */
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ldxa [%g0] ASI_SCRATCHPAD, %g3
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sub %g3, TRAP_PER_CPU_FAULT_INFO, %g3
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/* Get DEV mondo queue base phys address into %g5. */
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ldx [%g3 + TRAP_PER_CPU_DEV_MONDO_PA], %g5
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/* Load IVEC into %g3. */
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ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
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add %g2, 0x40, %g2
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/* XXX There can be a full 64-byte block of data here.
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* XXX This is how we can get at MSI vector data.
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* XXX Current we do not capture this, but when we do we'll
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* XXX need to add a 64-byte storage area in the struct ino_bucket
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* XXX or the struct irq_desc.
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*/
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/* Update queue head pointer, this frees up some registers. */
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sethi %hi(8192 - 1), %g4
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or %g4, %lo(8192 - 1), %g4
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and %g2, %g4, %g2
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mov INTRQ_DEVICE_MONDO_HEAD, %g4
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stxa %g2, [%g4] ASI_QUEUE
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membar #Sync
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/* Get &__irq_work[smp_processor_id()] into %g1. */
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TRAP_LOAD_IRQ_WORK(%g1, %g4)
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/* Get &ivector_table[IVEC] into %g4. */
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sethi %hi(ivector_table), %g4
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sllx %g3, 5, %g3
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or %g4, %lo(ivector_table), %g4
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add %g4, %g3, %g4
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/* Load IRQ %pil into %g5. */
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ldub [%g4 + 0x04], %g5
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/* Insert ivector_table[] entry into __irq_work[] queue. */
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sllx %g5, 2, %g3
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lduw [%g1 + %g3], %g2 /* g2 = irq_work(cpu, pil) */
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stw %g2, [%g4 + 0x00] /* bucket->irq_chain = g2 */
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stw %g4, [%g1 + %g3] /* irq_work(cpu, pil) = bucket */
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/* Signal the interrupt by setting (1 << pil) in %softint. */
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mov 1, %g2
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sllx %g2, %g5, %g2
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wr %g2, 0x0, %set_softint
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sun4v_dev_mondo_queue_empty:
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retry
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sun4v_res_mondo:
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/* Head offset in %g2, tail offset in %g4. */
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mov INTRQ_RESUM_MONDO_HEAD, %g2
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ldxa [%g2] ASI_QUEUE, %g2
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mov INTRQ_RESUM_MONDO_TAIL, %g4
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ldxa [%g4] ASI_QUEUE, %g4
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cmp %g2, %g4
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be,pn %xcc, sun4v_res_mondo_queue_empty
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nop
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/* Get &trap_block[smp_processor_id()] into %g3. */
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ldxa [%g0] ASI_SCRATCHPAD, %g3
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sub %g3, TRAP_PER_CPU_FAULT_INFO, %g3
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/* Get RES mondo queue base phys address into %g5. */
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ldx [%g3 + TRAP_PER_CPU_RESUM_MONDO_PA], %g5
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/* Get RES kernel buffer base phys address into %g7. */
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ldx [%g3 + TRAP_PER_CPU_RESUM_KBUF_PA], %g7
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/* If the first word is non-zero, queue is full. */
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ldxa [%g7 + %g2] ASI_PHYS_USE_EC, %g1
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brnz,pn %g1, sun4v_res_mondo_queue_full
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nop
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/* Remember this entry's offset in %g1. */
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mov %g2, %g1
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/* Copy 64-byte queue entry into kernel buffer. */
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ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
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stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
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add %g2, 0x08, %g2
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ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
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stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
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add %g2, 0x08, %g2
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ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
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stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
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add %g2, 0x08, %g2
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ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
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stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
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add %g2, 0x08, %g2
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ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
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stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
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add %g2, 0x08, %g2
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ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
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stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
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add %g2, 0x08, %g2
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ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
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stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
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add %g2, 0x08, %g2
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ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
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stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
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add %g2, 0x08, %g2
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/* Update queue head pointer. */
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sethi %hi(8192 - 1), %g4
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or %g4, %lo(8192 - 1), %g4
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and %g2, %g4, %g2
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mov INTRQ_RESUM_MONDO_HEAD, %g4
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stxa %g2, [%g4] ASI_QUEUE
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membar #Sync
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/* Disable interrupts and save register state so we can call
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* C code. The etrap handling will leave %g4 in %l4 for us
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* when it's done.
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*/
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rdpr %pil, %g2
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wrpr %g0, 15, %pil
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mov %g1, %g4
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ba,pt %xcc, etrap_irq
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rd %pc, %g7
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/* Log the event. */
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add %sp, PTREGS_OFF, %o0
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call sun4v_resum_error
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mov %l4, %o1
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/* Return from trap. */
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ba,pt %xcc, rtrap_irq
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nop
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sun4v_res_mondo_queue_empty:
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retry
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sun4v_res_mondo_queue_full:
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/* The queue is full, consolidate our damage by setting
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* the head equal to the tail. We'll just trap again otherwise.
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* Call C code to log the event.
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*/
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mov INTRQ_RESUM_MONDO_HEAD, %g2
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stxa %g4, [%g2] ASI_QUEUE
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membar #Sync
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rdpr %pil, %g2
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wrpr %g0, 15, %pil
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ba,pt %xcc, etrap_irq
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rd %pc, %g7
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call sun4v_resum_overflow
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add %sp, PTREGS_OFF, %o0
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ba,pt %xcc, rtrap_irq
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nop
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sun4v_nonres_mondo:
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/* Head offset in %g2, tail offset in %g4. */
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mov INTRQ_NONRESUM_MONDO_HEAD, %g2
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ldxa [%g2] ASI_QUEUE, %g2
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mov INTRQ_NONRESUM_MONDO_TAIL, %g4
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ldxa [%g4] ASI_QUEUE, %g4
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cmp %g2, %g4
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be,pn %xcc, sun4v_nonres_mondo_queue_empty
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nop
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/* Get &trap_block[smp_processor_id()] into %g3. */
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ldxa [%g0] ASI_SCRATCHPAD, %g3
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sub %g3, TRAP_PER_CPU_FAULT_INFO, %g3
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/* Get RES mondo queue base phys address into %g5. */
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ldx [%g3 + TRAP_PER_CPU_NONRESUM_MONDO_PA], %g5
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/* Get RES kernel buffer base phys address into %g7. */
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ldx [%g3 + TRAP_PER_CPU_NONRESUM_KBUF_PA], %g7
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/* If the first word is non-zero, queue is full. */
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ldxa [%g7 + %g2] ASI_PHYS_USE_EC, %g1
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brnz,pn %g1, sun4v_nonres_mondo_queue_full
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nop
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/* Remember this entry's offset in %g1. */
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mov %g2, %g1
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/* Copy 64-byte queue entry into kernel buffer. */
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ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
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stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
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add %g2, 0x08, %g2
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ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
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stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
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add %g2, 0x08, %g2
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ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
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stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
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add %g2, 0x08, %g2
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ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
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stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
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add %g2, 0x08, %g2
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ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
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stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
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add %g2, 0x08, %g2
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ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
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stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
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add %g2, 0x08, %g2
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ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
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stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
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add %g2, 0x08, %g2
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ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
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stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
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add %g2, 0x08, %g2
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/* Update queue head pointer. */
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sethi %hi(8192 - 1), %g4
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or %g4, %lo(8192 - 1), %g4
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and %g2, %g4, %g2
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mov INTRQ_NONRESUM_MONDO_HEAD, %g4
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stxa %g2, [%g4] ASI_QUEUE
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membar #Sync
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/* Disable interrupts and save register state so we can call
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* C code. The etrap handling will leave %g4 in %l4 for us
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* when it's done.
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*/
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rdpr %pil, %g2
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wrpr %g0, 15, %pil
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mov %g1, %g4
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ba,pt %xcc, etrap_irq
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rd %pc, %g7
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/* Log the event. */
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add %sp, PTREGS_OFF, %o0
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call sun4v_nonresum_error
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mov %l4, %o1
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/* Return from trap. */
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ba,pt %xcc, rtrap_irq
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nop
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sun4v_nonres_mondo_queue_empty:
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retry
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sun4v_nonres_mondo_queue_full:
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/* The queue is full, consolidate our damage by setting
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* the head equal to the tail. We'll just trap again otherwise.
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* Call C code to log the event.
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*/
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mov INTRQ_NONRESUM_MONDO_HEAD, %g2
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stxa %g4, [%g2] ASI_QUEUE
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membar #Sync
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rdpr %pil, %g2
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wrpr %g0, 15, %pil
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ba,pt %xcc, etrap_irq
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rd %pc, %g7
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call sun4v_nonresum_overflow
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add %sp, PTREGS_OFF, %o0
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ba,pt %xcc, rtrap_irq
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nop
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