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Dick Fowles, Don Zickus and Joe Mario have been working on improvements to perf, and noticed heavy cache line contention on the mm_cpumask, running linpack on a 60 core / 120 thread system. The cause turned out to be unnecessary atomic accesses to the mm_cpumask. When in lazy TLB mode, the CPU is only removed from the mm_cpumask if there is a TLB flush event. Most of the time, no such TLB flush happens, and the kernel skips the TLB reload. It can also skip the atomic memory set & test. Here is a summary of Joe's test results: * The __schedule function dropped from 24% of all program cycles down to 5.5%. * The cacheline contention/hotness for accesses to that bitmask went from being the 1st/2nd hottest - down to the 84th hottest (0.3% of all shared misses which is now quite cold) * The average load latency for the bit-test-n-set instruction in __schedule dropped from 10k-15k cycles down to an average of 600 cycles. * The linpack program results improved from 133 GFlops to 144 GFlops. Peak GFlops rose from 133 to 153. Reported-by: Don Zickus <dzickus@redhat.com> Reported-by: Joe Mario <jmario@redhat.com> Tested-by: Joe Mario <jmario@redhat.com> Signed-off-by: Rik van Riel <riel@redhat.com> Reviewed-by: Paul Turner <pjt@google.com> Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Link: http://lkml.kernel.org/r/20130731221421.616d3d20@annuminas.surriel.com [ Made the comments consistent around the modified code. ] Signed-off-by: Ingo Molnar <mingo@kernel.org>
100 lines
2.4 KiB
C
100 lines
2.4 KiB
C
#ifndef _ASM_X86_MMU_CONTEXT_H
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#define _ASM_X86_MMU_CONTEXT_H
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#include <asm/desc.h>
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#include <linux/atomic.h>
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#include <asm/pgalloc.h>
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#include <asm/tlbflush.h>
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#include <asm/paravirt.h>
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#ifndef CONFIG_PARAVIRT
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#include <asm-generic/mm_hooks.h>
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static inline void paravirt_activate_mm(struct mm_struct *prev,
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struct mm_struct *next)
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{
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}
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#endif /* !CONFIG_PARAVIRT */
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/*
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* Used for LDT copy/destruction.
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*/
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int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
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void destroy_context(struct mm_struct *mm);
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static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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#ifdef CONFIG_SMP
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if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
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this_cpu_write(cpu_tlbstate.state, TLBSTATE_LAZY);
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#endif
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}
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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unsigned cpu = smp_processor_id();
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if (likely(prev != next)) {
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#ifdef CONFIG_SMP
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this_cpu_write(cpu_tlbstate.state, TLBSTATE_OK);
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this_cpu_write(cpu_tlbstate.active_mm, next);
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#endif
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cpumask_set_cpu(cpu, mm_cpumask(next));
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/* Re-load page tables */
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load_cr3(next->pgd);
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/* Stop flush ipis for the previous mm */
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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/* Load the LDT, if the LDT is different: */
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if (unlikely(prev->context.ldt != next->context.ldt))
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load_LDT_nolock(&next->context);
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}
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#ifdef CONFIG_SMP
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else {
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this_cpu_write(cpu_tlbstate.state, TLBSTATE_OK);
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BUG_ON(this_cpu_read(cpu_tlbstate.active_mm) != next);
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if (!cpumask_test_cpu(cpu, mm_cpumask(next))) {
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/*
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* On established mms, the mm_cpumask is only changed
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* from irq context, from ptep_clear_flush() while in
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* lazy tlb mode, and here. Irqs are blocked during
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* schedule, protecting us from simultaneous changes.
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*/
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cpumask_set_cpu(cpu, mm_cpumask(next));
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/*
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* We were in lazy tlb mode and leave_mm disabled
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* tlb flush IPI delivery. We must reload CR3
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* to make sure to use no freed page tables.
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*/
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load_cr3(next->pgd);
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load_LDT_nolock(&next->context);
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}
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}
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#endif
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}
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#define activate_mm(prev, next) \
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do { \
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paravirt_activate_mm((prev), (next)); \
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switch_mm((prev), (next), NULL); \
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} while (0);
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#ifdef CONFIG_X86_32
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#define deactivate_mm(tsk, mm) \
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do { \
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lazy_load_gs(0); \
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} while (0)
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#else
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#define deactivate_mm(tsk, mm) \
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do { \
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load_gs_index(0); \
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loadsegment(fs, 0); \
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} while (0)
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#endif
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#endif /* _ASM_X86_MMU_CONTEXT_H */
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