Michal Simek 9c749e177c microblaze: Fix unaligned issue on MMU system with BS=0 DIV=1 ... Unaligned code use shift for finding register operand. There is used BSRLI(r8,r8,2) macro which is expand for BS=0, DIV=1 by ori rD, r0, (1 << imm); \ idivu rD, rD, rA but if rD is equal rA then ori instruction rewrite value which should be devide. The patch remove this macro which use idivu instruction because idivu takes 32/34 cycles. The highest shifting is 20 which takes 20 cycles. Signed-off-by: Michal Simek <monstr@monstr.eu>		2011-01-28 14:05:00 +01:00
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boot	microblaze/of: Use generic rule to build dtb's	2010-12-23 14:59:52 -07:00
configs	kconfig: rename CONFIG_EMBEDDED to CONFIG_EXPERT	2011-01-20 17:02:05 -08:00
include/asm	microblaze: Fix asm/pgtable.h	2011-01-16 14:29:41 +01:00
kernel	microblaze: Fix unaligned issue on MMU system with BS=0 DIV=1	2011-01-28 14:05:00 +01:00
lib	microblaze: Fix __muldi3 function for little-endian.	2011-01-03 10:30:31 +01:00
mm	memblock, microblaze: Fix memblock API change fallout	2010-09-11 10:30:28 +02:00
oprofile	microblaze: Core oprofile configs and hooks	2009-12-14 08:45:07 +01:00
pci	microblaze: pci-common cleanup	2010-10-21 15:51:54 +10:00
platform	microblaze: Add PVR for endians plus detection	2010-10-21 15:51:57 +10:00
Kconfig	microblaze: Use generic irq Kconfig	2011-01-21 11:55:32 +01:00
Kconfig.debug	microblaze: remove obsolete DEBUG_BOOTMEM	2011-01-10 09:29:51 +01:00
Makefile	microblaze: trivial: Fix removed the part of line	2011-01-03 11:36:32 +01:00