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9c2af6c57c
Add support for the Shiva 88fr131 CPU core as found in e.g. the Marvell Kirkwood family of ARM SoCs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
631 lines
16 KiB
ArmAsm
631 lines
16 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
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*
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* Heavily based on proc-arm926.S
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* Maintainer: Assaf Hoffman <hoffman@marvell.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/elf.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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/*
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* This is the maximum size of an area which will be invalidated
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* using the single invalidate entry instructions. Anything larger
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* than this, and we go for the whole cache.
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*
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* This value should be chosen such that we choose the cheapest
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* alternative.
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*/
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#define CACHE_DLIMIT 16384
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/*
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* the cache line size of the I and D cache
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*/
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#define CACHE_DLINESIZE 32
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.bss
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.align 3
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__cache_params_loc:
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.space 8
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.text
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__cache_params:
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.word __cache_params_loc
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/*
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* cpu_feroceon_proc_init()
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*/
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ENTRY(cpu_feroceon_proc_init)
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mrc p15, 0, r0, c0, c0, 1 @ read cache type register
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ldr r1, __cache_params
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mov r2, #(16 << 5)
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tst r0, #(1 << 16) @ get way
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mov r0, r0, lsr #18 @ get cache size order
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movne r3, #((4 - 1) << 30) @ 4-way
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and r0, r0, #0xf
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moveq r3, #0 @ 1-way
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mov r2, r2, lsl r0 @ actual cache size
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movne r2, r2, lsr #2 @ turned into # of sets
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sub r2, r2, #(1 << 5)
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stmia r1, {r2, r3}
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mov pc, lr
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/*
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* cpu_feroceon_proc_fin()
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*/
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ENTRY(cpu_feroceon_proc_fin)
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stmfd sp!, {lr}
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mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
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msr cpsr_c, ip
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bl feroceon_flush_kern_cache_all
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#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
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mov r0, #0
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mcr p15, 1, r0, c15, c9, 0 @ clean L2
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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#endif
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x000e @ ............wca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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ldmfd sp!, {pc}
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/*
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* cpu_feroceon_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* loc: location to jump to for soft reset
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*/
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.align 5
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ENTRY(cpu_feroceon_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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/*
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* cpu_feroceon_do_idle()
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*
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* Called with IRQs disabled
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*/
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.align 5
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ENTRY(cpu_feroceon_do_idle)
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
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mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
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mov pc, lr
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/*
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* flush_user_cache_all()
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*
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* Clean and invalidate all cache entries in a particular
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* address space.
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*/
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.align 5
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ENTRY(feroceon_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(feroceon_flush_kern_cache_all)
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mov r2, #VM_EXEC
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__flush_whole_cache:
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ldr r1, __cache_params
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ldmia r1, {r1, r3}
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1: orr ip, r1, r3
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2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
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subs ip, ip, #(1 << 30) @ next way
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bcs 2b
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subs r1, r1, #(1 << 5) @ next set
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bcs 1b
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tst r2, #VM_EXEC
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mov ip, #0
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Clean and invalidate a range of cache entries in the
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* specified address range.
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*
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* - start - start address (inclusive)
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* - end - end address (exclusive)
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* - flags - vm_flags describing address space
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*/
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.align 5
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ENTRY(feroceon_flush_user_cache_range)
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sub r3, r1, r0 @ calculate total size
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cmp r3, #CACHE_DLIMIT
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bgt __flush_whole_cache
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1: tst r2, #VM_EXEC
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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tst r2, #VM_EXEC
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mov ip, #0
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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.align 5
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ENTRY(feroceon_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(feroceon_coherent_user_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* flush_kern_dcache_page(void *page)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - addr - page aligned address
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*/
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.align 5
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ENTRY(feroceon_flush_kern_dcache_page)
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add r1, r0, #PAGE_SZ
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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.align 5
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ENTRY(feroceon_range_flush_kern_dcache_page)
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mrs r2, cpsr
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add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive
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orr r3, r2, #PSR_I_BIT
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msr cpsr_c, r3 @ disable interrupts
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mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
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mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
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msr cpsr_c, r2 @ restore interrupts
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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.align 5
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ENTRY(feroceon_dma_inv_range)
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tst r0, #CACHE_DLINESIZE - 1
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bic r0, r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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.align 5
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ENTRY(feroceon_range_dma_inv_range)
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mrs r2, cpsr
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tst r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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cmp r1, r0
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subne r1, r1, #1 @ top address is inclusive
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orr r3, r2, #PSR_I_BIT
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msr cpsr_c, r3 @ disable interrupts
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mcr p15, 5, r0, c15, c14, 0 @ D inv range start
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mcr p15, 5, r1, c15, c14, 1 @ D inv range top
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msr cpsr_c, r2 @ restore interrupts
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mov pc, lr
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/*
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* dma_clean_range(start, end)
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*
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* Clean the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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.align 5
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ENTRY(feroceon_dma_clean_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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.align 5
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ENTRY(feroceon_range_dma_clean_range)
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mrs r2, cpsr
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cmp r1, r0
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subne r1, r1, #1 @ top address is inclusive
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orr r3, r2, #PSR_I_BIT
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msr cpsr_c, r3 @ disable interrupts
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mcr p15, 5, r0, c15, c13, 0 @ D clean range start
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mcr p15, 5, r1, c15, c13, 1 @ D clean range top
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msr cpsr_c, r2 @ restore interrupts
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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.align 5
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ENTRY(feroceon_dma_flush_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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.align 5
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ENTRY(feroceon_range_dma_flush_range)
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mrs r2, cpsr
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cmp r1, r0
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subne r1, r1, #1 @ top address is inclusive
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orr r3, r2, #PSR_I_BIT
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msr cpsr_c, r3 @ disable interrupts
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mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
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mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
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msr cpsr_c, r2 @ restore interrupts
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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ENTRY(feroceon_cache_fns)
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.long feroceon_flush_kern_cache_all
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.long feroceon_flush_user_cache_all
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.long feroceon_flush_user_cache_range
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.long feroceon_coherent_kern_range
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.long feroceon_coherent_user_range
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.long feroceon_flush_kern_dcache_page
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.long feroceon_dma_inv_range
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.long feroceon_dma_clean_range
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.long feroceon_dma_flush_range
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ENTRY(feroceon_range_cache_fns)
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.long feroceon_flush_kern_cache_all
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.long feroceon_flush_user_cache_all
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.long feroceon_flush_user_cache_range
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.long feroceon_coherent_kern_range
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.long feroceon_coherent_user_range
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.long feroceon_range_flush_kern_dcache_page
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.long feroceon_range_dma_inv_range
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.long feroceon_range_dma_clean_range
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.long feroceon_range_dma_flush_range
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.align 5
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ENTRY(cpu_feroceon_dcache_clean_area)
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#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
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mov r2, r0
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mov r3, r1
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#endif
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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subs r1, r1, #CACHE_DLINESIZE
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bhi 1b
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#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
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1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry
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add r2, r2, #CACHE_DLINESIZE
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subs r3, r3, #CACHE_DLINESIZE
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bhi 1b
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#endif
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/* =============================== PageTable ============================== */
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/*
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* cpu_feroceon_switch_mm(pgd)
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*
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* Set the translation base pointer to be as described by pgd.
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*
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* pgd: new page tables
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*/
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.align 5
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ENTRY(cpu_feroceon_switch_mm)
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#ifdef CONFIG_MMU
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/*
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* Note: we wish to call __flush_whole_cache but we need to preserve
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* lr to do so. The only way without touching main memory is to
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* use r2 which is normally used to test the VM_EXEC flag, and
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* compensate locally for the skipped ops if it is not set.
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*/
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mov r2, lr @ abuse r2 to preserve lr
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bl __flush_whole_cache
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@ if r2 contains the VM_EXEC bit then the next 2 ops are done already
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tst r2, #VM_EXEC
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mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcreq p15, 0, ip, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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mov pc, r2
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#else
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mov pc, lr
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#endif
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/*
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* cpu_feroceon_set_pte_ext(ptep, pte, ext)
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*
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* Set a PTE and flush it out
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*/
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.align 5
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ENTRY(cpu_feroceon_set_pte_ext)
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#ifdef CONFIG_MMU
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str r1, [r0], #-2048 @ linux version
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eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
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bic r2, r1, #PTE_SMALL_AP_MASK
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bic r2, r2, #PTE_TYPE_MASK
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orr r2, r2, #PTE_TYPE_SMALL
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tst r1, #L_PTE_USER @ User?
|
|
orrne r2, r2, #PTE_SMALL_AP_URO_SRW
|
|
|
|
tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
|
|
orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
|
|
|
|
tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
|
|
movne r2, #0
|
|
|
|
str r2, [r0] @ hardware version
|
|
mov r0, r0
|
|
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
|
#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
|
|
mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry
|
|
#endif
|
|
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
|
#endif
|
|
mov pc, lr
|
|
|
|
__INIT
|
|
|
|
.type __feroceon_setup, #function
|
|
__feroceon_setup:
|
|
mov r0, #0
|
|
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
|
|
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
|
|
#ifdef CONFIG_MMU
|
|
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
|
|
#endif
|
|
|
|
adr r5, feroceon_crval
|
|
ldmia r5, {r5, r6}
|
|
mrc p15, 0, r0, c1, c0 @ get control register v4
|
|
bic r0, r0, r5
|
|
orr r0, r0, r6
|
|
mov pc, lr
|
|
.size __feroceon_setup, . - __feroceon_setup
|
|
|
|
/*
|
|
* R
|
|
* .RVI ZFRS BLDP WCAM
|
|
* .011 0001 ..11 0101
|
|
*
|
|
*/
|
|
.type feroceon_crval, #object
|
|
feroceon_crval:
|
|
crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
|
|
|
|
__INITDATA
|
|
|
|
/*
|
|
* Purpose : Function pointers used to access above functions - all calls
|
|
* come through these
|
|
*/
|
|
.type feroceon_processor_functions, #object
|
|
feroceon_processor_functions:
|
|
.word v5t_early_abort
|
|
.word pabort_noifar
|
|
.word cpu_feroceon_proc_init
|
|
.word cpu_feroceon_proc_fin
|
|
.word cpu_feroceon_reset
|
|
.word cpu_feroceon_do_idle
|
|
.word cpu_feroceon_dcache_clean_area
|
|
.word cpu_feroceon_switch_mm
|
|
.word cpu_feroceon_set_pte_ext
|
|
.size feroceon_processor_functions, . - feroceon_processor_functions
|
|
|
|
.section ".rodata"
|
|
|
|
.type cpu_arch_name, #object
|
|
cpu_arch_name:
|
|
.asciz "armv5te"
|
|
.size cpu_arch_name, . - cpu_arch_name
|
|
|
|
.type cpu_elf_name, #object
|
|
cpu_elf_name:
|
|
.asciz "v5"
|
|
.size cpu_elf_name, . - cpu_elf_name
|
|
|
|
.type cpu_feroceon_name, #object
|
|
cpu_feroceon_name:
|
|
.asciz "Feroceon"
|
|
.size cpu_feroceon_name, . - cpu_feroceon_name
|
|
|
|
.type cpu_88fr531_name, #object
|
|
cpu_88fr531_name:
|
|
.asciz "Feroceon 88FR531-vd"
|
|
.size cpu_88fr531_name, . - cpu_88fr531_name
|
|
|
|
.type cpu_88fr131_name, #object
|
|
cpu_88fr131_name:
|
|
.asciz "Feroceon 88FR131"
|
|
.size cpu_88fr131_name, . - cpu_88fr131_name
|
|
|
|
.align
|
|
|
|
.section ".proc.info.init", #alloc, #execinstr
|
|
|
|
#ifdef CONFIG_CPU_FEROCEON_OLD_ID
|
|
.type __feroceon_old_id_proc_info,#object
|
|
__feroceon_old_id_proc_info:
|
|
.long 0x41009260
|
|
.long 0xff00fff0
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_BIT4 | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_BIT4 | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __feroceon_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_feroceon_name
|
|
.long feroceon_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long feroceon_user_fns
|
|
.long feroceon_cache_fns
|
|
.size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
|
|
#endif
|
|
|
|
.type __88fr531_proc_info,#object
|
|
__88fr531_proc_info:
|
|
.long 0x56055310
|
|
.long 0xfffffff0
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_BIT4 | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_BIT4 | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __feroceon_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_88fr531_name
|
|
.long feroceon_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long feroceon_user_fns
|
|
.long feroceon_cache_fns
|
|
.size __88fr531_proc_info, . - __88fr531_proc_info
|
|
|
|
.type __88fr131_proc_info,#object
|
|
__88fr131_proc_info:
|
|
.long 0x56251310
|
|
.long 0xfffffff0
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_BIT4 | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_BIT4 | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __feroceon_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_88fr131_name
|
|
.long feroceon_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long feroceon_user_fns
|
|
.long feroceon_range_cache_fns
|
|
.size __88fr131_proc_info, . - __88fr131_proc_info
|