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9b454d16e5
imx25 contains two registers (LPIMR0 and 1) to define which interrupts are enabled in low-power mode. As of today, those two registers are configured to enable all interrupts. Before going to low-power mode, the AVIC's INTENABLEH and INTENABLEL registers are configured to enable only those interrupts which are used as wakeup sources. It turned out that this approach is not sufficient if we want the imx25 to go into stop mode during suspend-to-ram. (Stop mode is the low-power mode that consumes the least power. The peripheral master clock is switched off in this mode). For stop mode to work, the LPIMR0 and 1 registers have to be configured with the set of interrupts that are allowed in low-power mode. Fortunately, the bits in the LPIMR registers are assigned to the same interrupts as the bits in INTENABLEH and INTENABLEL. However, LPIMR uses 1 to mask an interrupt whereas the INTENABLE registers use 1 to enable an interrupt. This patch sets the LPIMR registers to the inverted bitmask of the INTENABLE registers during suspend and goes back to "all interrupts masked" when we wake up again. We also make this the default at startup. As far as I know, the other supported imx architectures have no similar mechanism. Since the LPIMR registers are part of the CCM module, we query the device tree for an imx25 ccm node in order to detect if we're running on imx25. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Signed-off-by: Shawn Guo <shawnguo@kernel.org> |
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