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Currently, when the physical resume CPU is not equal to the physical suspend CPU, we swap the CPUs logically, by modifying the logical/physical CPU mapping. This has two major drawbacks: First the change is visible from user space (e.g. CPU sysfs files) and second it is hard to ensure that nowhere in the kernel the physical CPU ID is stored before suspend. To fix this, we now really swap the physical CPUs, if the resume CPU is not the pysical suspend CPU. We restart the suspend CPU and stop the resume CPU using SIGP restart and SIGP stop. If the suspend CPU is no longer available, we write a message and load a disabled wait PSW. Signed-off-by: Michael Holzheu <michael.holzheu@linux.vnet.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
464 lines
14 KiB
C
464 lines
14 KiB
C
/*
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* include/asm-s390/lowcore.h
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*
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* S390 version
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* Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
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* Author(s): Hartmut Penner (hp@de.ibm.com),
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* Martin Schwidefsky (schwidefsky@de.ibm.com),
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* Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
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*/
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#ifndef _ASM_S390_LOWCORE_H
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#define _ASM_S390_LOWCORE_H
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#define __LC_IPL_PARMBLOCK_PTR 0x0014
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#define __LC_EXT_PARAMS 0x0080
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#define __LC_CPU_ADDRESS 0x0084
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#define __LC_EXT_INT_CODE 0x0086
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#define __LC_SVC_ILC 0x0088
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#define __LC_SVC_INT_CODE 0x008a
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#define __LC_PGM_ILC 0x008c
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#define __LC_PGM_INT_CODE 0x008e
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#define __LC_PER_ATMID 0x0096
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#define __LC_PER_ADDRESS 0x0098
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#define __LC_PER_ACCESS_ID 0x00a1
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#define __LC_AR_MODE_ID 0x00a3
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#define __LC_SUBCHANNEL_ID 0x00b8
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#define __LC_SUBCHANNEL_NR 0x00ba
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#define __LC_IO_INT_PARM 0x00bc
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#define __LC_IO_INT_WORD 0x00c0
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#define __LC_STFL_FAC_LIST 0x00c8
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#define __LC_MCCK_CODE 0x00e8
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#define __LC_DUMP_REIPL 0x0e00
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#ifndef __s390x__
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#define __LC_EXT_OLD_PSW 0x0018
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#define __LC_SVC_OLD_PSW 0x0020
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#define __LC_PGM_OLD_PSW 0x0028
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#define __LC_MCK_OLD_PSW 0x0030
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#define __LC_IO_OLD_PSW 0x0038
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#define __LC_EXT_NEW_PSW 0x0058
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#define __LC_SVC_NEW_PSW 0x0060
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#define __LC_PGM_NEW_PSW 0x0068
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#define __LC_MCK_NEW_PSW 0x0070
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#define __LC_IO_NEW_PSW 0x0078
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#define __LC_SAVE_AREA 0x0200
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#define __LC_RETURN_PSW 0x0240
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#define __LC_RETURN_MCCK_PSW 0x0248
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#define __LC_SYNC_ENTER_TIMER 0x0250
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#define __LC_ASYNC_ENTER_TIMER 0x0258
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#define __LC_EXIT_TIMER 0x0260
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#define __LC_USER_TIMER 0x0268
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#define __LC_SYSTEM_TIMER 0x0270
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#define __LC_STEAL_TIMER 0x0278
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#define __LC_LAST_UPDATE_TIMER 0x0280
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#define __LC_LAST_UPDATE_CLOCK 0x0288
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#define __LC_CURRENT 0x0290
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#define __LC_THREAD_INFO 0x0294
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#define __LC_KERNEL_STACK 0x0298
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#define __LC_ASYNC_STACK 0x029c
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#define __LC_PANIC_STACK 0x02a0
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#define __LC_KERNEL_ASCE 0x02a4
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#define __LC_USER_ASCE 0x02a8
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#define __LC_USER_EXEC_ASCE 0x02ac
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#define __LC_CPUID 0x02b0
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#define __LC_INT_CLOCK 0x02c8
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#define __LC_MACHINE_FLAGS 0x02d8
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#define __LC_FTRACE_FUNC 0x02dc
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#define __LC_IRB 0x0300
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#define __LC_PFAULT_INTPARM 0x0080
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#define __LC_CPU_TIMER_SAVE_AREA 0x00d8
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#define __LC_CLOCK_COMP_SAVE_AREA 0x00e0
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#define __LC_PSW_SAVE_AREA 0x0100
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#define __LC_PREFIX_SAVE_AREA 0x0108
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#define __LC_AREGS_SAVE_AREA 0x0120
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#define __LC_FPREGS_SAVE_AREA 0x0160
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#define __LC_GPREGS_SAVE_AREA 0x0180
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#define __LC_CREGS_SAVE_AREA 0x01c0
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#else /* __s390x__ */
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#define __LC_LAST_BREAK 0x0110
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#define __LC_EXT_OLD_PSW 0x0130
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#define __LC_SVC_OLD_PSW 0x0140
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#define __LC_PGM_OLD_PSW 0x0150
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#define __LC_MCK_OLD_PSW 0x0160
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#define __LC_IO_OLD_PSW 0x0170
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#define __LC_RESTART_PSW 0x01a0
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#define __LC_EXT_NEW_PSW 0x01b0
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#define __LC_SVC_NEW_PSW 0x01c0
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#define __LC_PGM_NEW_PSW 0x01d0
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#define __LC_MCK_NEW_PSW 0x01e0
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#define __LC_IO_NEW_PSW 0x01f0
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#define __LC_SAVE_AREA 0x0200
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#define __LC_RETURN_PSW 0x0280
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#define __LC_RETURN_MCCK_PSW 0x0290
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#define __LC_SYNC_ENTER_TIMER 0x02a0
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#define __LC_ASYNC_ENTER_TIMER 0x02a8
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#define __LC_EXIT_TIMER 0x02b0
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#define __LC_USER_TIMER 0x02b8
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#define __LC_SYSTEM_TIMER 0x02c0
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#define __LC_STEAL_TIMER 0x02c8
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#define __LC_LAST_UPDATE_TIMER 0x02d0
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#define __LC_LAST_UPDATE_CLOCK 0x02d8
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#define __LC_CURRENT 0x02e0
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#define __LC_THREAD_INFO 0x02e8
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#define __LC_KERNEL_STACK 0x02f0
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#define __LC_ASYNC_STACK 0x02f8
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#define __LC_PANIC_STACK 0x0300
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#define __LC_KERNEL_ASCE 0x0308
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#define __LC_USER_ASCE 0x0310
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#define __LC_USER_EXEC_ASCE 0x0318
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#define __LC_CPUID 0x0320
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#define __LC_INT_CLOCK 0x0340
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#define __LC_VDSO_PER_CPU 0x0350
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#define __LC_MACHINE_FLAGS 0x0358
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#define __LC_FTRACE_FUNC 0x0360
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#define __LC_IRB 0x0380
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#define __LC_PASTE 0x03c0
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#define __LC_PFAULT_INTPARM 0x11b8
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#define __LC_FPREGS_SAVE_AREA 0x1200
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#define __LC_GPREGS_SAVE_AREA 0x1280
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#define __LC_PSW_SAVE_AREA 0x1300
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#define __LC_PREFIX_SAVE_AREA 0x1318
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#define __LC_FP_CREG_SAVE_AREA 0x131c
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#define __LC_TODREG_SAVE_AREA 0x1324
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#define __LC_CPU_TIMER_SAVE_AREA 0x1328
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#define __LC_CLOCK_COMP_SAVE_AREA 0x1331
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#define __LC_AREGS_SAVE_AREA 0x1340
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#define __LC_CREGS_SAVE_AREA 0x1380
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#endif /* __s390x__ */
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#ifndef __ASSEMBLY__
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#include <asm/cpu.h>
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#include <asm/ptrace.h>
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#include <linux/types.h>
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void restart_int_handler(void);
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void ext_int_handler(void);
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void system_call(void);
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void pgm_check_handler(void);
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void mcck_int_handler(void);
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void io_int_handler(void);
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struct save_area_s390 {
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u32 ext_save;
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u64 timer;
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u64 clk_cmp;
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u8 pad1[24];
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u8 psw[8];
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u32 pref_reg;
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u8 pad2[20];
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u32 acc_regs[16];
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u64 fp_regs[4];
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u32 gp_regs[16];
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u32 ctrl_regs[16];
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} __attribute__((packed));
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struct save_area_s390x {
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u64 fp_regs[16];
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u64 gp_regs[16];
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u8 psw[16];
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u8 pad1[8];
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u32 pref_reg;
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u32 fp_ctrl_reg;
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u8 pad2[4];
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u32 tod_reg;
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u64 timer;
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u64 clk_cmp;
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u8 pad3[8];
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u32 acc_regs[16];
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u64 ctrl_regs[16];
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} __attribute__((packed));
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union save_area {
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struct save_area_s390 s390;
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struct save_area_s390x s390x;
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};
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#define SAVE_AREA_BASE_S390 0xd4
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#define SAVE_AREA_BASE_S390X 0x1200
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#ifndef __s390x__
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#define SAVE_AREA_SIZE sizeof(struct save_area_s390)
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#define SAVE_AREA_BASE SAVE_AREA_BASE_S390
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#else
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#define SAVE_AREA_SIZE sizeof(struct save_area_s390x)
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#define SAVE_AREA_BASE SAVE_AREA_BASE_S390X
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#endif
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#ifndef __s390x__
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#define LC_ORDER 0
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#else
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#define LC_ORDER 1
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#endif
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#define LC_PAGES (1UL << LC_ORDER)
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struct _lowcore
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{
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#ifndef __s390x__
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/* 0x0000 - 0x01ff: defined by architecture */
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psw_t restart_psw; /* 0x0000 */
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__u32 ccw2[4]; /* 0x0008 */
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psw_t external_old_psw; /* 0x0018 */
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psw_t svc_old_psw; /* 0x0020 */
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psw_t program_old_psw; /* 0x0028 */
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psw_t mcck_old_psw; /* 0x0030 */
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psw_t io_old_psw; /* 0x0038 */
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__u8 pad_0x0040[0x0058-0x0040]; /* 0x0040 */
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psw_t external_new_psw; /* 0x0058 */
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psw_t svc_new_psw; /* 0x0060 */
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psw_t program_new_psw; /* 0x0068 */
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psw_t mcck_new_psw; /* 0x0070 */
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psw_t io_new_psw; /* 0x0078 */
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__u32 ext_params; /* 0x0080 */
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__u16 cpu_addr; /* 0x0084 */
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__u16 ext_int_code; /* 0x0086 */
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__u16 svc_ilc; /* 0x0088 */
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__u16 svc_code; /* 0x008a */
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__u16 pgm_ilc; /* 0x008c */
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__u16 pgm_code; /* 0x008e */
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__u32 trans_exc_code; /* 0x0090 */
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__u16 mon_class_num; /* 0x0094 */
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__u16 per_perc_atmid; /* 0x0096 */
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__u32 per_address; /* 0x0098 */
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__u32 monitor_code; /* 0x009c */
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__u8 exc_access_id; /* 0x00a0 */
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__u8 per_access_id; /* 0x00a1 */
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__u8 pad_0x00a2[0x00b8-0x00a2]; /* 0x00a2 */
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__u16 subchannel_id; /* 0x00b8 */
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__u16 subchannel_nr; /* 0x00ba */
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__u32 io_int_parm; /* 0x00bc */
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__u32 io_int_word; /* 0x00c0 */
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__u8 pad_0x00c4[0x00c8-0x00c4]; /* 0x00c4 */
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__u32 stfl_fac_list; /* 0x00c8 */
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__u8 pad_0x00cc[0x00d4-0x00cc]; /* 0x00cc */
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__u32 extended_save_area_addr; /* 0x00d4 */
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__u32 cpu_timer_save_area[2]; /* 0x00d8 */
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__u32 clock_comp_save_area[2]; /* 0x00e0 */
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__u32 mcck_interruption_code[2]; /* 0x00e8 */
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__u8 pad_0x00f0[0x00f4-0x00f0]; /* 0x00f0 */
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__u32 external_damage_code; /* 0x00f4 */
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__u32 failing_storage_address; /* 0x00f8 */
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__u8 pad_0x00fc[0x0100-0x00fc]; /* 0x00fc */
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__u32 st_status_fixed_logout[4]; /* 0x0100 */
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__u8 pad_0x0110[0x0120-0x0110]; /* 0x0110 */
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/* CPU register save area: defined by architecture */
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__u32 access_regs_save_area[16]; /* 0x0120 */
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__u32 floating_pt_save_area[8]; /* 0x0160 */
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__u32 gpregs_save_area[16]; /* 0x0180 */
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__u32 cregs_save_area[16]; /* 0x01c0 */
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/* Return psws. */
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__u32 save_area[16]; /* 0x0200 */
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psw_t return_psw; /* 0x0240 */
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psw_t return_mcck_psw; /* 0x0248 */
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/* CPU time accounting values */
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__u64 sync_enter_timer; /* 0x0250 */
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__u64 async_enter_timer; /* 0x0258 */
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__u64 exit_timer; /* 0x0260 */
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__u64 user_timer; /* 0x0268 */
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__u64 system_timer; /* 0x0270 */
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__u64 steal_timer; /* 0x0278 */
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__u64 last_update_timer; /* 0x0280 */
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__u64 last_update_clock; /* 0x0288 */
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/* Current process. */
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__u32 current_task; /* 0x0290 */
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__u32 thread_info; /* 0x0294 */
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__u32 kernel_stack; /* 0x0298 */
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/* Interrupt and panic stack. */
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__u32 async_stack; /* 0x029c */
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__u32 panic_stack; /* 0x02a0 */
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/* Address space pointer. */
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__u32 kernel_asce; /* 0x02a4 */
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__u32 user_asce; /* 0x02a8 */
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__u32 user_exec_asce; /* 0x02ac */
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/* SMP info area */
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struct cpuid cpu_id; /* 0x02b0 */
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__u32 cpu_nr; /* 0x02b8 */
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__u32 softirq_pending; /* 0x02bc */
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__u32 percpu_offset; /* 0x02c0 */
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__u32 ext_call_fast; /* 0x02c4 */
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__u64 int_clock; /* 0x02c8 */
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__u64 clock_comparator; /* 0x02d0 */
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__u32 machine_flags; /* 0x02d8 */
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__u32 ftrace_func; /* 0x02dc */
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__u8 pad_0x02f0[0x0300-0x02f0]; /* 0x02f0 */
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/* Interrupt response block */
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__u8 irb[64]; /* 0x0300 */
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__u8 pad_0x0400[0x0e00-0x0400]; /* 0x0400 */
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/*
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* 0xe00 contains the address of the IPL Parameter Information
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* block. Dump tools need IPIB for IPL after dump.
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* Note: do not change the position of any fields in 0x0e00-0x0f00
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*/
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__u32 ipib; /* 0x0e00 */
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__u32 ipib_checksum; /* 0x0e04 */
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/* Align to the top 1k of prefix area */
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__u8 pad_0x0e08[0x1000-0x0e08]; /* 0x0e08 */
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#else /* !__s390x__ */
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/* 0x0000 - 0x01ff: defined by architecture */
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__u32 ccw1[2]; /* 0x0000 */
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__u32 ccw2[4]; /* 0x0008 */
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__u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */
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__u32 ext_params; /* 0x0080 */
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__u16 cpu_addr; /* 0x0084 */
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__u16 ext_int_code; /* 0x0086 */
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__u16 svc_ilc; /* 0x0088 */
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__u16 svc_code; /* 0x008a */
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__u16 pgm_ilc; /* 0x008c */
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__u16 pgm_code; /* 0x008e */
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__u32 data_exc_code; /* 0x0090 */
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__u16 mon_class_num; /* 0x0094 */
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__u16 per_perc_atmid; /* 0x0096 */
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addr_t per_address; /* 0x0098 */
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__u8 exc_access_id; /* 0x00a0 */
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__u8 per_access_id; /* 0x00a1 */
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__u8 op_access_id; /* 0x00a2 */
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__u8 ar_access_id; /* 0x00a3 */
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__u8 pad_0x00a4[0x00a8-0x00a4]; /* 0x00a4 */
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addr_t trans_exc_code; /* 0x00a8 */
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addr_t monitor_code; /* 0x00b0 */
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__u16 subchannel_id; /* 0x00b8 */
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__u16 subchannel_nr; /* 0x00ba */
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__u32 io_int_parm; /* 0x00bc */
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__u32 io_int_word; /* 0x00c0 */
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__u8 pad_0x00c4[0x00c8-0x00c4]; /* 0x00c4 */
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__u32 stfl_fac_list; /* 0x00c8 */
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__u8 pad_0x00cc[0x00e8-0x00cc]; /* 0x00cc */
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__u32 mcck_interruption_code[2]; /* 0x00e8 */
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__u8 pad_0x00f0[0x00f4-0x00f0]; /* 0x00f0 */
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__u32 external_damage_code; /* 0x00f4 */
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addr_t failing_storage_address; /* 0x00f8 */
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__u8 pad_0x0100[0x0120-0x0100]; /* 0x0100 */
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psw_t restart_old_psw; /* 0x0120 */
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psw_t external_old_psw; /* 0x0130 */
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psw_t svc_old_psw; /* 0x0140 */
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psw_t program_old_psw; /* 0x0150 */
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psw_t mcck_old_psw; /* 0x0160 */
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psw_t io_old_psw; /* 0x0170 */
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__u8 pad_0x0180[0x01a0-0x0180]; /* 0x0180 */
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psw_t restart_psw; /* 0x01a0 */
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psw_t external_new_psw; /* 0x01b0 */
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psw_t svc_new_psw; /* 0x01c0 */
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psw_t program_new_psw; /* 0x01d0 */
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psw_t mcck_new_psw; /* 0x01e0 */
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psw_t io_new_psw; /* 0x01f0 */
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/* Entry/exit save area & return psws. */
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__u64 save_area[16]; /* 0x0200 */
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psw_t return_psw; /* 0x0280 */
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psw_t return_mcck_psw; /* 0x0290 */
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/* CPU accounting and timing values. */
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__u64 sync_enter_timer; /* 0x02a0 */
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__u64 async_enter_timer; /* 0x02a8 */
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__u64 exit_timer; /* 0x02b0 */
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__u64 user_timer; /* 0x02b8 */
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__u64 system_timer; /* 0x02c0 */
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__u64 steal_timer; /* 0x02c8 */
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__u64 last_update_timer; /* 0x02d0 */
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__u64 last_update_clock; /* 0x02d8 */
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/* Current process. */
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__u64 current_task; /* 0x02e0 */
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__u64 thread_info; /* 0x02e8 */
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__u64 kernel_stack; /* 0x02f0 */
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/* Interrupt and panic stack. */
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__u64 async_stack; /* 0x02f8 */
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|
__u64 panic_stack; /* 0x0300 */
|
|
|
|
/* Address space pointer. */
|
|
__u64 kernel_asce; /* 0x0308 */
|
|
__u64 user_asce; /* 0x0310 */
|
|
__u64 user_exec_asce; /* 0x0318 */
|
|
|
|
/* SMP info area */
|
|
struct cpuid cpu_id; /* 0x0320 */
|
|
__u32 cpu_nr; /* 0x0328 */
|
|
__u32 softirq_pending; /* 0x032c */
|
|
__u64 percpu_offset; /* 0x0330 */
|
|
__u64 ext_call_fast; /* 0x0338 */
|
|
__u64 int_clock; /* 0x0340 */
|
|
__u64 clock_comparator; /* 0x0348 */
|
|
__u64 vdso_per_cpu_data; /* 0x0350 */
|
|
__u64 machine_flags; /* 0x0358 */
|
|
__u64 ftrace_func; /* 0x0360 */
|
|
__u8 pad_0x0368[0x0380-0x0368]; /* 0x0368 */
|
|
|
|
/* Interrupt response block. */
|
|
__u8 irb[64]; /* 0x0380 */
|
|
|
|
/* Per cpu primary space access list */
|
|
__u32 paste[16]; /* 0x03c0 */
|
|
|
|
__u8 pad_0x0400[0x0e00-0x0400]; /* 0x0400 */
|
|
|
|
/*
|
|
* 0xe00 contains the address of the IPL Parameter Information
|
|
* block. Dump tools need IPIB for IPL after dump.
|
|
* Note: do not change the position of any fields in 0x0e00-0x0f00
|
|
*/
|
|
__u64 ipib; /* 0x0e00 */
|
|
__u32 ipib_checksum; /* 0x0e08 */
|
|
__u8 pad_0x0e0c[0x11b8-0x0e0c]; /* 0x0e0c */
|
|
|
|
/* 64 bit extparam used for pfault/diag 250: defined by architecture */
|
|
__u64 ext_params2; /* 0x11B8 */
|
|
__u8 pad_0x11c0[0x1200-0x11C0]; /* 0x11C0 */
|
|
|
|
/* CPU register save area: defined by architecture */
|
|
__u64 floating_pt_save_area[16]; /* 0x1200 */
|
|
__u64 gpregs_save_area[16]; /* 0x1280 */
|
|
__u32 st_status_fixed_logout[4]; /* 0x1300 */
|
|
__u8 pad_0x1310[0x1318-0x1310]; /* 0x1310 */
|
|
__u32 prefixreg_save_area; /* 0x1318 */
|
|
__u32 fpt_creg_save_area; /* 0x131c */
|
|
__u8 pad_0x1320[0x1324-0x1320]; /* 0x1320 */
|
|
__u32 tod_progreg_save_area; /* 0x1324 */
|
|
__u32 cpu_timer_save_area[2]; /* 0x1328 */
|
|
__u32 clock_comp_save_area[2]; /* 0x1330 */
|
|
__u8 pad_0x1338[0x1340-0x1338]; /* 0x1338 */
|
|
__u32 access_regs_save_area[16]; /* 0x1340 */
|
|
__u64 cregs_save_area[16]; /* 0x1380 */
|
|
|
|
/* align to the top of the prefix area */
|
|
__u8 pad_0x1400[0x2000-0x1400]; /* 0x1400 */
|
|
#endif /* !__s390x__ */
|
|
} __attribute__((packed)); /* End structure*/
|
|
|
|
#define S390_lowcore (*((struct _lowcore *) 0))
|
|
extern struct _lowcore *lowcore_ptr[];
|
|
|
|
static inline void set_prefix(__u32 address)
|
|
{
|
|
asm volatile("spx %0" : : "m" (address) : "memory");
|
|
}
|
|
|
|
static inline __u32 store_prefix(void)
|
|
{
|
|
__u32 address;
|
|
|
|
asm volatile("stpx %0" : "=m" (address));
|
|
return address;
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif
|