mirror of
https://github.com/torvalds/linux.git
synced 2024-11-11 14:42:24 +00:00
2d5e447914
Audio Tracking Logic is designed to be used by HD Radio applications to synchronize the audio output clocks to the baseband clock. ATL can be also used to track errors between two reference clocks (BWS, AWS) and generate a modulated clock output which averages to some desired frequency. In essence ATL is generating a clock to be used by an audio codec and also to be used by the SoC as MCLK. To be able to integrate the ATL provided clocks to the clock tree we need two types of DT binding: - DT clock nodes to represent the ATL clocks towards the CCF - binding for the ATL IP itself which is going to handle the hw configuration The reason for this type of setup is that ATL itself is a separate device in the SoC, it has it's own address space and clock domain. Other IPs can use the ATL generated clock as their functional clock (McASPs for example) and external components like audio codecs can also use the very same clock as their MCLK. The ATL IP in DRA7 contains 4 ATL instences. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
41 lines
1.3 KiB
C
41 lines
1.3 KiB
C
/*
|
|
* This header provides constants for DRA7 ATL (Audio Tracking Logic)
|
|
*
|
|
* The constants defined in this header are used in dts files
|
|
*
|
|
* Copyright (C) 2013 Texas Instruments, Inc.
|
|
*
|
|
* Peter Ujfalusi <peter.ujfalusi@ti.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
|
* kind, whether express or implied; without even the implied warranty
|
|
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H
|
|
#define _DT_BINDINGS_CLK_DRA7_ATL_H
|
|
|
|
#define DRA7_ATL_WS_MCASP1_FSR 0
|
|
#define DRA7_ATL_WS_MCASP1_FSX 1
|
|
#define DRA7_ATL_WS_MCASP2_FSR 2
|
|
#define DRA7_ATL_WS_MCASP2_FSX 3
|
|
#define DRA7_ATL_WS_MCASP3_FSX 4
|
|
#define DRA7_ATL_WS_MCASP4_FSX 5
|
|
#define DRA7_ATL_WS_MCASP5_FSX 6
|
|
#define DRA7_ATL_WS_MCASP6_FSX 7
|
|
#define DRA7_ATL_WS_MCASP7_FSX 8
|
|
#define DRA7_ATL_WS_MCASP8_FSX 9
|
|
#define DRA7_ATL_WS_MCASP8_AHCLKX 10
|
|
#define DRA7_ATL_WS_XREF_CLK3 11
|
|
#define DRA7_ATL_WS_XREF_CLK0 12
|
|
#define DRA7_ATL_WS_XREF_CLK1 13
|
|
#define DRA7_ATL_WS_XREF_CLK2 14
|
|
#define DRA7_ATL_WS_OSC1_X1 15
|
|
|
|
#endif
|