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040f6b4f14
Use the current PIO mode value instead of the physical maximum one of the pair device on the port to determine PIO commmand timings used for both devices on the port. Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
643 lines
17 KiB
C
643 lines
17 KiB
C
/*
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* TX4939 internal IDE driver
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* Based on RBTX49xx patch from CELF patch archive.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* (C) Copyright TOSHIBA CORPORATION 2005-2007
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/ide.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/scatterlist.h>
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#include <asm/ide.h>
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#define MODNAME "tx4939ide"
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/* ATA Shadow Registers (8-bit except for Data which is 16-bit) */
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#define TX4939IDE_Data 0x000
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#define TX4939IDE_Error_Feature 0x001
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#define TX4939IDE_Sec 0x002
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#define TX4939IDE_LBA0 0x003
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#define TX4939IDE_LBA1 0x004
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#define TX4939IDE_LBA2 0x005
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#define TX4939IDE_DevHead 0x006
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#define TX4939IDE_Stat_Cmd 0x007
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#define TX4939IDE_AltStat_DevCtl 0x402
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/* H/W DMA Registers */
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#define TX4939IDE_DMA_Cmd 0x800 /* 8-bit */
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#define TX4939IDE_DMA_Stat 0x802 /* 8-bit */
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#define TX4939IDE_PRD_Ptr 0x804 /* 32-bit */
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/* ATA100 CORE Registers (16-bit) */
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#define TX4939IDE_Sys_Ctl 0xc00
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#define TX4939IDE_Xfer_Cnt_1 0xc08
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#define TX4939IDE_Xfer_Cnt_2 0xc0a
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#define TX4939IDE_Sec_Cnt 0xc10
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#define TX4939IDE_Start_Lo_Addr 0xc18
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#define TX4939IDE_Start_Up_Addr 0xc20
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#define TX4939IDE_Add_Ctl 0xc28
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#define TX4939IDE_Lo_Burst_Cnt 0xc30
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#define TX4939IDE_Up_Burst_Cnt 0xc38
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#define TX4939IDE_PIO_Addr 0xc88
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#define TX4939IDE_H_Rst_Tim 0xc90
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#define TX4939IDE_Int_Ctl 0xc98
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#define TX4939IDE_Pkt_Cmd 0xcb8
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#define TX4939IDE_Bxfer_Cnt_Hi 0xcc0
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#define TX4939IDE_Bxfer_Cnt_Lo 0xcc8
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#define TX4939IDE_Dev_TErr 0xcd0
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#define TX4939IDE_Pkt_Xfer_Ctl 0xcd8
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#define TX4939IDE_Start_TAddr 0xce0
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/* bits for Int_Ctl */
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#define TX4939IDE_INT_ADDRERR 0x80
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#define TX4939IDE_INT_REACHMUL 0x40
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#define TX4939IDE_INT_DEVTIMING 0x20
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#define TX4939IDE_INT_UDMATERM 0x10
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#define TX4939IDE_INT_TIMER 0x08
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#define TX4939IDE_INT_BUSERR 0x04
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#define TX4939IDE_INT_XFEREND 0x02
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#define TX4939IDE_INT_HOST 0x01
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#define TX4939IDE_IGNORE_INTS \
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(TX4939IDE_INT_ADDRERR | TX4939IDE_INT_REACHMUL | \
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TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_UDMATERM | \
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TX4939IDE_INT_TIMER | TX4939IDE_INT_XFEREND)
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#ifdef __BIG_ENDIAN
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#define tx4939ide_swizzlel(a) ((a) ^ 4)
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#define tx4939ide_swizzlew(a) ((a) ^ 6)
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#define tx4939ide_swizzleb(a) ((a) ^ 7)
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#else
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#define tx4939ide_swizzlel(a) (a)
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#define tx4939ide_swizzlew(a) (a)
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#define tx4939ide_swizzleb(a) (a)
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#endif
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static u16 tx4939ide_readw(void __iomem *base, u32 reg)
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{
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return __raw_readw(base + tx4939ide_swizzlew(reg));
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}
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static u8 tx4939ide_readb(void __iomem *base, u32 reg)
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{
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return __raw_readb(base + tx4939ide_swizzleb(reg));
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}
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static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg)
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{
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__raw_writel(val, base + tx4939ide_swizzlel(reg));
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}
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static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg)
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{
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__raw_writew(val, base + tx4939ide_swizzlew(reg));
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}
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static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg)
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{
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__raw_writeb(val, base + tx4939ide_swizzleb(reg));
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}
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#define TX4939IDE_BASE(hwif) ((void __iomem *)(hwif)->extra_base)
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static void tx4939ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
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{
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int is_slave = drive->dn;
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u32 mask, val;
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const u8 pio = drive->pio_mode - XFER_PIO_0;
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u8 safe = pio;
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ide_drive_t *pair;
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pair = ide_get_pair_dev(drive);
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if (pair)
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safe = min(safe, pair->pio_mode - XFER_PIO_0);
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/*
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* Update Command Transfer Mode for master/slave and Data
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* Transfer Mode for this drive.
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*/
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mask = is_slave ? 0x07f00000 : 0x000007f0;
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val = ((safe << 8) | (pio << 4)) << (is_slave ? 16 : 0);
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hwif->select_data = (hwif->select_data & ~mask) | val;
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/* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
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}
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static void tx4939ide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
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{
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u32 mask, val;
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const u8 mode = drive->dma_mode;
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/* Update Data Transfer Mode for this drive. */
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if (mode >= XFER_UDMA_0)
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val = mode - XFER_UDMA_0 + 8;
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else
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val = mode - XFER_MW_DMA_0 + 5;
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if (drive->dn) {
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mask = 0x00f00000;
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val <<= 20;
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} else {
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mask = 0x000000f0;
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val <<= 4;
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}
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hwif->select_data = (hwif->select_data & ~mask) | val;
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/* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
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}
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static u16 tx4939ide_check_error_ints(ide_hwif_t *hwif)
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{
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void __iomem *base = TX4939IDE_BASE(hwif);
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u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl);
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if (ctl & TX4939IDE_INT_BUSERR) {
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/* reset FIFO */
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u16 sysctl = tx4939ide_readw(base, TX4939IDE_Sys_Ctl);
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tx4939ide_writew(sysctl | 0x4000, base, TX4939IDE_Sys_Ctl);
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mmiowb();
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/* wait 12GBUSCLK (typ. 60ns @ GBUS200MHz, max 270ns) */
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ndelay(270);
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tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
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}
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if (ctl & (TX4939IDE_INT_ADDRERR |
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TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_BUSERR))
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pr_err("%s: Error interrupt %#x (%s%s%s )\n",
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hwif->name, ctl,
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ctl & TX4939IDE_INT_ADDRERR ? " Address-Error" : "",
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ctl & TX4939IDE_INT_DEVTIMING ? " DEV-Timing" : "",
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ctl & TX4939IDE_INT_BUSERR ? " Bus-Error" : "");
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return ctl;
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}
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static void tx4939ide_clear_irq(ide_drive_t *drive)
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{
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ide_hwif_t *hwif;
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void __iomem *base;
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u16 ctl;
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/*
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* tx4939ide_dma_test_irq() and tx4939ide_dma_end() do all job
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* for DMA case.
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*/
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if (drive->waiting_for_dma)
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return;
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hwif = drive->hwif;
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base = TX4939IDE_BASE(hwif);
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ctl = tx4939ide_check_error_ints(hwif);
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tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl);
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}
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static u8 tx4939ide_cable_detect(ide_hwif_t *hwif)
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{
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void __iomem *base = TX4939IDE_BASE(hwif);
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return tx4939ide_readw(base, TX4939IDE_Sys_Ctl) & 0x2000 ?
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ATA_CBL_PATA40 : ATA_CBL_PATA80;
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}
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#ifdef __BIG_ENDIAN
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static void tx4939ide_dma_host_set(ide_drive_t *drive, int on)
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{
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ide_hwif_t *hwif = drive->hwif;
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u8 unit = drive->dn;
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void __iomem *base = TX4939IDE_BASE(hwif);
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u8 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
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if (on)
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dma_stat |= (1 << (5 + unit));
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else
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dma_stat &= ~(1 << (5 + unit));
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tx4939ide_writeb(dma_stat, base, TX4939IDE_DMA_Stat);
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}
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#else
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#define tx4939ide_dma_host_set ide_dma_host_set
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#endif
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static u8 tx4939ide_clear_dma_status(void __iomem *base)
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{
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u8 dma_stat;
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/* read DMA status for INTR & ERROR flags */
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dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
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/* clear INTR & ERROR flags */
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tx4939ide_writeb(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, base,
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TX4939IDE_DMA_Stat);
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/* recover intmask cleared by writing to bit2 of DMA_Stat */
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tx4939ide_writew(TX4939IDE_IGNORE_INTS << 8, base, TX4939IDE_Int_Ctl);
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return dma_stat;
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}
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#ifdef __BIG_ENDIAN
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/* custom ide_build_dmatable to handle swapped layout */
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static int tx4939ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
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{
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ide_hwif_t *hwif = drive->hwif;
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u32 *table = (u32 *)hwif->dmatable_cpu;
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unsigned int count = 0;
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int i;
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struct scatterlist *sg;
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for_each_sg(hwif->sg_table, sg, cmd->sg_nents, i) {
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u32 cur_addr, cur_len, bcount;
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cur_addr = sg_dma_address(sg);
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cur_len = sg_dma_len(sg);
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/*
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* Fill in the DMA table, without crossing any 64kB boundaries.
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*/
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while (cur_len) {
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if (count++ >= PRD_ENTRIES)
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goto use_pio_instead;
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bcount = 0x10000 - (cur_addr & 0xffff);
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if (bcount > cur_len)
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bcount = cur_len;
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/*
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* This workaround for zero count seems required.
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* (standard ide_build_dmatable does it too)
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*/
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if (bcount == 0x10000)
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bcount = 0x8000;
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*table++ = bcount & 0xffff;
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*table++ = cur_addr;
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cur_addr += bcount;
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cur_len -= bcount;
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}
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}
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if (count) {
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*(table - 2) |= 0x80000000;
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return count;
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}
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use_pio_instead:
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printk(KERN_ERR "%s: %s\n", drive->name,
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count ? "DMA table too small" : "empty DMA table?");
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return 0; /* revert to PIO for this request */
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}
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#else
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#define tx4939ide_build_dmatable ide_build_dmatable
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#endif
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static int tx4939ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
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{
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ide_hwif_t *hwif = drive->hwif;
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void __iomem *base = TX4939IDE_BASE(hwif);
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u8 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR;
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/* fall back to PIO! */
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if (tx4939ide_build_dmatable(drive, cmd) == 0)
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return 1;
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/* PRD table */
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tx4939ide_writel(hwif->dmatable_dma, base, TX4939IDE_PRD_Ptr);
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/* specify r/w */
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tx4939ide_writeb(rw, base, TX4939IDE_DMA_Cmd);
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/* clear INTR & ERROR flags */
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tx4939ide_clear_dma_status(base);
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tx4939ide_writew(SECTOR_SIZE / 2, base, drive->dn ?
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TX4939IDE_Xfer_Cnt_2 : TX4939IDE_Xfer_Cnt_1);
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tx4939ide_writew(blk_rq_sectors(cmd->rq), base, TX4939IDE_Sec_Cnt);
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return 0;
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}
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static int tx4939ide_dma_end(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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u8 dma_stat, dma_cmd;
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void __iomem *base = TX4939IDE_BASE(hwif);
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u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl);
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/* get DMA command mode */
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dma_cmd = tx4939ide_readb(base, TX4939IDE_DMA_Cmd);
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/* stop DMA */
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tx4939ide_writeb(dma_cmd & ~ATA_DMA_START, base, TX4939IDE_DMA_Cmd);
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/* read and clear the INTR & ERROR bits */
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dma_stat = tx4939ide_clear_dma_status(base);
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#define CHECK_DMA_MASK (ATA_DMA_ACTIVE | ATA_DMA_ERR | ATA_DMA_INTR)
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/* verify good DMA status */
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if ((dma_stat & CHECK_DMA_MASK) == 0 &&
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(ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) ==
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(TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST))
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/* INT_IDE lost... bug? */
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return 0;
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return ((dma_stat & CHECK_DMA_MASK) !=
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ATA_DMA_INTR) ? 0x10 | dma_stat : 0;
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}
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/* returns 1 if DMA IRQ issued, 0 otherwise */
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static int tx4939ide_dma_test_irq(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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void __iomem *base = TX4939IDE_BASE(hwif);
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u16 ctl, ide_int;
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u8 dma_stat, stat;
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int found = 0;
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ctl = tx4939ide_check_error_ints(hwif);
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ide_int = ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST);
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switch (ide_int) {
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case TX4939IDE_INT_HOST:
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/* On error, XFEREND might not be asserted. */
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stat = tx4939ide_readb(base, TX4939IDE_AltStat_DevCtl);
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if ((stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) == ATA_ERR)
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found = 1;
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else
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/* Wait for XFEREND (Mask HOST and unmask XFEREND) */
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ctl &= ~TX4939IDE_INT_XFEREND << 8;
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ctl |= ide_int << 8;
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break;
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case TX4939IDE_INT_HOST | TX4939IDE_INT_XFEREND:
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dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
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if (!(dma_stat & ATA_DMA_INTR))
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pr_warning("%s: weird interrupt status. "
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"DMA_Stat %#02x int_ctl %#04x\n",
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hwif->name, dma_stat, ctl);
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found = 1;
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break;
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}
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/*
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* Do not clear XFEREND, HOST now. They will be cleared by
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* clearing bit2 of DMA_Stat.
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*/
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ctl &= ~ide_int;
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tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl);
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return found;
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}
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#ifdef __BIG_ENDIAN
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static u8 tx4939ide_dma_sff_read_status(ide_hwif_t *hwif)
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{
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void __iomem *base = TX4939IDE_BASE(hwif);
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return tx4939ide_readb(base, TX4939IDE_DMA_Stat);
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}
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#else
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#define tx4939ide_dma_sff_read_status ide_dma_sff_read_status
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#endif
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static void tx4939ide_init_hwif(ide_hwif_t *hwif)
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{
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void __iomem *base = TX4939IDE_BASE(hwif);
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/* Soft Reset */
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tx4939ide_writew(0x8000, base, TX4939IDE_Sys_Ctl);
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mmiowb();
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/* at least 20 GBUSCLK (typ. 100ns @ GBUS200MHz, max 450ns) */
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ndelay(450);
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tx4939ide_writew(0x0000, base, TX4939IDE_Sys_Ctl);
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/* mask some interrupts and clear all interrupts */
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tx4939ide_writew((TX4939IDE_IGNORE_INTS << 8) | 0xff, base,
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TX4939IDE_Int_Ctl);
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tx4939ide_writew(0x0008, base, TX4939IDE_Lo_Burst_Cnt);
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tx4939ide_writew(0, base, TX4939IDE_Up_Burst_Cnt);
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}
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static int tx4939ide_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
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{
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hwif->dma_base =
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hwif->extra_base + tx4939ide_swizzleb(TX4939IDE_DMA_Cmd);
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/*
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* Note that we cannot use ATA_DMA_TABLE_OFS, ATA_DMA_STATUS
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* for big endian.
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*/
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return ide_allocate_dma_engine(hwif);
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}
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static void tx4939ide_tf_load_fixup(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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void __iomem *base = TX4939IDE_BASE(hwif);
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u16 sysctl = hwif->select_data >> (drive->dn ? 16 : 0);
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/*
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* Fix ATA100 CORE System Control Register. (The write to the
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* Device/Head register may write wrong data to the System
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* Control Register)
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* While Sys_Ctl is written here, dev_select() is not needed.
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*/
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tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
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}
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static void tx4939ide_tf_load(ide_drive_t *drive, struct ide_taskfile *tf,
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u8 valid)
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{
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ide_tf_load(drive, tf, valid);
|
|
|
|
if (valid & IDE_VALID_DEVICE)
|
|
tx4939ide_tf_load_fixup(drive);
|
|
}
|
|
|
|
#ifdef __BIG_ENDIAN
|
|
|
|
/* custom iops (independent from SWAP_IO_SPACE) */
|
|
static void tx4939ide_input_data_swap(ide_drive_t *drive, struct ide_cmd *cmd,
|
|
void *buf, unsigned int len)
|
|
{
|
|
unsigned long port = drive->hwif->io_ports.data_addr;
|
|
unsigned short *ptr = buf;
|
|
unsigned int count = (len + 1) / 2;
|
|
|
|
while (count--)
|
|
*ptr++ = cpu_to_le16(__raw_readw((void __iomem *)port));
|
|
__ide_flush_dcache_range((unsigned long)buf, roundup(len, 2));
|
|
}
|
|
|
|
static void tx4939ide_output_data_swap(ide_drive_t *drive, struct ide_cmd *cmd,
|
|
void *buf, unsigned int len)
|
|
{
|
|
unsigned long port = drive->hwif->io_ports.data_addr;
|
|
unsigned short *ptr = buf;
|
|
unsigned int count = (len + 1) / 2;
|
|
|
|
while (count--) {
|
|
__raw_writew(le16_to_cpu(*ptr), (void __iomem *)port);
|
|
ptr++;
|
|
}
|
|
__ide_flush_dcache_range((unsigned long)buf, roundup(len, 2));
|
|
}
|
|
|
|
static const struct ide_tp_ops tx4939ide_tp_ops = {
|
|
.exec_command = ide_exec_command,
|
|
.read_status = ide_read_status,
|
|
.read_altstatus = ide_read_altstatus,
|
|
.write_devctl = ide_write_devctl,
|
|
|
|
.dev_select = ide_dev_select,
|
|
.tf_load = tx4939ide_tf_load,
|
|
.tf_read = ide_tf_read,
|
|
|
|
.input_data = tx4939ide_input_data_swap,
|
|
.output_data = tx4939ide_output_data_swap,
|
|
};
|
|
|
|
#else /* __LITTLE_ENDIAN */
|
|
|
|
static const struct ide_tp_ops tx4939ide_tp_ops = {
|
|
.exec_command = ide_exec_command,
|
|
.read_status = ide_read_status,
|
|
.read_altstatus = ide_read_altstatus,
|
|
.write_devctl = ide_write_devctl,
|
|
|
|
.dev_select = ide_dev_select,
|
|
.tf_load = tx4939ide_tf_load,
|
|
.tf_read = ide_tf_read,
|
|
|
|
.input_data = ide_input_data,
|
|
.output_data = ide_output_data,
|
|
};
|
|
|
|
#endif /* __LITTLE_ENDIAN */
|
|
|
|
static const struct ide_port_ops tx4939ide_port_ops = {
|
|
.set_pio_mode = tx4939ide_set_pio_mode,
|
|
.set_dma_mode = tx4939ide_set_dma_mode,
|
|
.clear_irq = tx4939ide_clear_irq,
|
|
.cable_detect = tx4939ide_cable_detect,
|
|
};
|
|
|
|
static const struct ide_dma_ops tx4939ide_dma_ops = {
|
|
.dma_host_set = tx4939ide_dma_host_set,
|
|
.dma_setup = tx4939ide_dma_setup,
|
|
.dma_start = ide_dma_start,
|
|
.dma_end = tx4939ide_dma_end,
|
|
.dma_test_irq = tx4939ide_dma_test_irq,
|
|
.dma_lost_irq = ide_dma_lost_irq,
|
|
.dma_timer_expiry = ide_dma_sff_timer_expiry,
|
|
.dma_sff_read_status = tx4939ide_dma_sff_read_status,
|
|
};
|
|
|
|
static const struct ide_port_info tx4939ide_port_info __initdata = {
|
|
.init_hwif = tx4939ide_init_hwif,
|
|
.init_dma = tx4939ide_init_dma,
|
|
.port_ops = &tx4939ide_port_ops,
|
|
.dma_ops = &tx4939ide_dma_ops,
|
|
.tp_ops = &tx4939ide_tp_ops,
|
|
.host_flags = IDE_HFLAG_MMIO,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
.udma_mask = ATA_UDMA5,
|
|
.chipset = ide_generic,
|
|
};
|
|
|
|
static int __init tx4939ide_probe(struct platform_device *pdev)
|
|
{
|
|
struct ide_hw hw, *hws[] = { &hw };
|
|
struct ide_host *host;
|
|
struct resource *res;
|
|
int irq, ret;
|
|
unsigned long mapbase;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return -ENODEV;
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res)
|
|
return -ENODEV;
|
|
|
|
if (!devm_request_mem_region(&pdev->dev, res->start,
|
|
res->end - res->start + 1, "tx4938ide"))
|
|
return -EBUSY;
|
|
mapbase = (unsigned long)devm_ioremap(&pdev->dev, res->start,
|
|
res->end - res->start + 1);
|
|
if (!mapbase)
|
|
return -EBUSY;
|
|
memset(&hw, 0, sizeof(hw));
|
|
hw.io_ports.data_addr =
|
|
mapbase + tx4939ide_swizzlew(TX4939IDE_Data);
|
|
hw.io_ports.error_addr =
|
|
mapbase + tx4939ide_swizzleb(TX4939IDE_Error_Feature);
|
|
hw.io_ports.nsect_addr =
|
|
mapbase + tx4939ide_swizzleb(TX4939IDE_Sec);
|
|
hw.io_ports.lbal_addr =
|
|
mapbase + tx4939ide_swizzleb(TX4939IDE_LBA0);
|
|
hw.io_ports.lbam_addr =
|
|
mapbase + tx4939ide_swizzleb(TX4939IDE_LBA1);
|
|
hw.io_ports.lbah_addr =
|
|
mapbase + tx4939ide_swizzleb(TX4939IDE_LBA2);
|
|
hw.io_ports.device_addr =
|
|
mapbase + tx4939ide_swizzleb(TX4939IDE_DevHead);
|
|
hw.io_ports.command_addr =
|
|
mapbase + tx4939ide_swizzleb(TX4939IDE_Stat_Cmd);
|
|
hw.io_ports.ctl_addr =
|
|
mapbase + tx4939ide_swizzleb(TX4939IDE_AltStat_DevCtl);
|
|
hw.irq = irq;
|
|
hw.dev = &pdev->dev;
|
|
|
|
pr_info("TX4939 IDE interface (base %#lx, irq %d)\n", mapbase, irq);
|
|
host = ide_host_alloc(&tx4939ide_port_info, hws, 1);
|
|
if (!host)
|
|
return -ENOMEM;
|
|
/* use extra_base for base address of the all registers */
|
|
host->ports[0]->extra_base = mapbase;
|
|
ret = ide_host_register(host, &tx4939ide_port_info, hws);
|
|
if (ret) {
|
|
ide_host_free(host);
|
|
return ret;
|
|
}
|
|
platform_set_drvdata(pdev, host);
|
|
return 0;
|
|
}
|
|
|
|
static int __exit tx4939ide_remove(struct platform_device *pdev)
|
|
{
|
|
struct ide_host *host = platform_get_drvdata(pdev);
|
|
|
|
ide_host_remove(host);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int tx4939ide_resume(struct platform_device *dev)
|
|
{
|
|
struct ide_host *host = platform_get_drvdata(dev);
|
|
ide_hwif_t *hwif = host->ports[0];
|
|
|
|
tx4939ide_init_hwif(hwif);
|
|
return 0;
|
|
}
|
|
#else
|
|
#define tx4939ide_resume NULL
|
|
#endif
|
|
|
|
static struct platform_driver tx4939ide_driver = {
|
|
.driver = {
|
|
.name = MODNAME,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.remove = __exit_p(tx4939ide_remove),
|
|
.resume = tx4939ide_resume,
|
|
};
|
|
|
|
static int __init tx4939ide_init(void)
|
|
{
|
|
return platform_driver_probe(&tx4939ide_driver, tx4939ide_probe);
|
|
}
|
|
|
|
static void __exit tx4939ide_exit(void)
|
|
{
|
|
platform_driver_unregister(&tx4939ide_driver);
|
|
}
|
|
|
|
module_init(tx4939ide_init);
|
|
module_exit(tx4939ide_exit);
|
|
|
|
MODULE_DESCRIPTION("TX4939 internal IDE driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:tx4939ide");
|