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7e21774db5
entirely of new platform/driver support. There are some conversions of existing drivers to the common-clock Device Tree binding, and a few non-critical fixes to the framework. Due to an entirely unnecessary cyclical dependency with the arm-soc tree this pull request is broken into two pieces. The second piece will be sent out after arm-soc sends you the pull request that merged in core support for the HiSilicon 3620 platform. That same pull request from arm-soc depends on this pull request to merge in those HiSilicon bits without causing build failures. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJS4WZPAAoJEDqPOy9afJhJVz4QAL63xispjEVuABUjgskR1fyo 7QljpqUJCOViqiVqNi1sPtM0irvfrApNwTpK3mGm20/kbNIBSdqGc/fI5CbWxXAU scRqplTTLY6F7nXJXGgiM/e5b31Tb+KmY9Su5chq1Yv6py4/yb6SzoohcBlQJ5in JKIxgLqe1VqUkCY2EFlqLwYqUtgr/Zm6ZJDt4LTwxc43apwgG7USMAS8ppx7nTgd oGgcsU4dNur1L4+ahvwqC+ntfoZNmVKJm+eY+JrHXJ2sga4PLaJcorgK2NXFpgln nwZQzRfbZLg7vNg/ODIDvP94mhc266xq2TCWzD/kMOBwmhsM0lySpzI/IM8qv1U2 Tdy9EHAj2iHoU+s1yPEUtNRV4h2+BGUUy54690XO30+VCLVEJUCC2KopDAk0G3ua qxSCb1mJto8EEq3jCJwKZSOUI7gcizDjHAaqfLlnDytMlsFJR7AJVj5IcRdgC/9s Vg975Xklkn33fWEuYQzdQdcmJ8ZCnydo92R2S0CaMgxMZqp2eoYZXJWvgCAvfQYC HjAtnBpHxNsZQeASvclb9bQrEisAUjIrxvuzLenQhg88WhBuyUDgBdretCzHFhP4 i62QGAhSYiNJJQzs+U9EndG6fRr/p98Pmw2pBAAn8UYOT2wWMj8wpR+IVT50Bmdi j6LsDpvc7CE2a4f+KoCa =Hh66 -----END PGP SIGNATURE----- Merge tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux Pull clk framework changes from Mike Turquette: "The first half of the clk framework pull request is made up almost entirely of new platform/driver support. There are some conversions of existing drivers to the common-clock Device Tree binding, and a few non-critical fixes to the framework. Due to an entirely unnecessary cyclical dependency with the arm-soc tree this pull request is broken into two pieces. The second piece will be sent out after arm-soc sends you the pull request that merged in core support for the HiSilicon 3620 platform. That same pull request from arm-soc depends on this pull request to merge in those HiSilicon bits without causing build failures" [ Just did the ARM SoC merges, so getting ready for the second clk tree pull request - Linus ] * tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux: (97 commits) devicetree: bindings: Document qcom,mmcc devicetree: bindings: Document qcom,gcc clk: qcom: Add support for MSM8660's global clock controller (GCC) clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC) clk: qcom: Add support for MSM8974's global clock controller (GCC) clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC) clk: qcom: Add support for MSM8960's global clock controller (GCC) clk: qcom: Add reset controller support clk: qcom: Add support for branches/gate clocks clk: qcom: Add support for root clock generators (RCGs) clk: qcom: Add support for phase locked loops (PLLs) clk: qcom: Add a regmap type clock struct clk: Add set_rate_and_parent() op reset: Silence warning in reset-controller.h clk: sirf: re-arch to make the codes support both prima2 and atlas6 clk: composite: pass mux_hw into determine_rate clk: shmobile: Fix MSTP clock array initialization clk: shmobile: Fix MSTP clock index ARM: dts: Add clock provider specific properties to max77686 node clk: max77686: Register OF clock provider ...
656 lines
15 KiB
Plaintext
656 lines
15 KiB
Plaintext
/*
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* SAMSUNG EXYNOS5420 SoC device tree source
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*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
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* EXYNOS5420 based board files can include this file and provide
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* values for board specfic bindings.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "exynos5.dtsi"
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#include "exynos5420-pinctrl.dtsi"
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#include <dt-bindings/clk/exynos-audss-clk.h>
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/ {
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compatible = "samsung,exynos5420";
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aliases {
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mshc0 = &mmc_0;
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mshc1 = &mmc_1;
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mshc2 = &mmc_2;
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pinctrl0 = &pinctrl_0;
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pinctrl1 = &pinctrl_1;
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pinctrl2 = &pinctrl_2;
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pinctrl3 = &pinctrl_3;
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pinctrl4 = &pinctrl_4;
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i2c0 = &i2c_0;
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i2c1 = &i2c_1;
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i2c2 = &i2c_2;
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i2c3 = &i2c_3;
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i2c4 = &hsi2c_4;
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i2c5 = &hsi2c_5;
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i2c6 = &hsi2c_6;
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i2c7 = &hsi2c_7;
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i2c8 = &hsi2c_8;
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i2c9 = &hsi2c_9;
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i2c10 = &hsi2c_10;
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gsc0 = &gsc_0;
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gsc1 = &gsc_1;
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spi0 = &spi_0;
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spi1 = &spi_1;
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spi2 = &spi_2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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clock-frequency = <1800000000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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clock-frequency = <1800000000>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x2>;
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clock-frequency = <1800000000>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x3>;
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clock-frequency = <1800000000>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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clock-frequency = <1000000000>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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clock-frequency = <1000000000>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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clock-frequency = <1000000000>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x103>;
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clock-frequency = <1000000000>;
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};
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};
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clock: clock-controller@10010000 {
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compatible = "samsung,exynos5420-clock";
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reg = <0x10010000 0x30000>;
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#clock-cells = <1>;
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};
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clock_audss: audss-clock-controller@3810000 {
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compatible = "samsung,exynos5420-audss-clock";
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reg = <0x03810000 0x0C>;
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#clock-cells = <1>;
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clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>;
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clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
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};
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codec@11000000 {
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compatible = "samsung,mfc-v7";
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reg = <0x11000000 0x10000>;
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interrupts = <0 96 0>;
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clocks = <&clock 401>;
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clock-names = "mfc";
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};
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mmc_0: mmc@12200000 {
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compatible = "samsung,exynos5420-dw-mshc-smu";
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interrupts = <0 75 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x12200000 0x2000>;
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clocks = <&clock 351>, <&clock 132>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x40>;
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status = "disabled";
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};
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mmc_1: mmc@12210000 {
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compatible = "samsung,exynos5420-dw-mshc-smu";
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interrupts = <0 76 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x12210000 0x2000>;
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clocks = <&clock 352>, <&clock 133>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x40>;
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status = "disabled";
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};
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mmc_2: mmc@12220000 {
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compatible = "samsung,exynos5420-dw-mshc";
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interrupts = <0 77 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x12220000 0x1000>;
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clocks = <&clock 353>, <&clock 134>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x40>;
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status = "disabled";
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};
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mct@101C0000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x101C0000 0x800>;
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interrupt-controller;
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#interrups-cells = <1>;
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interrupt-parent = <&mct_map>;
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interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
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<8>, <9>, <10>, <11>;
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clocks = <&clock 1>, <&clock 315>;
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clock-names = "fin_pll", "mct";
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mct_map: mct-map {
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = <0 &combiner 23 3>,
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<1 &combiner 23 4>,
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<2 &combiner 25 2>,
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<3 &combiner 25 3>,
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<4 &gic 0 120 0>,
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<5 &gic 0 121 0>,
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<6 &gic 0 122 0>,
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<7 &gic 0 123 0>,
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<8 &gic 0 128 0>,
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<9 &gic 0 129 0>,
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<10 &gic 0 130 0>,
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<11 &gic 0 131 0>;
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};
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};
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gsc_pd: power-domain@10044000 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044000 0x20>;
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};
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isp_pd: power-domain@10044020 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044020 0x20>;
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};
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mfc_pd: power-domain@10044060 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044060 0x20>;
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};
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disp_pd: power-domain@100440C0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x100440C0 0x20>;
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};
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mau_pd: power-domain@100440E0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x100440E0 0x20>;
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};
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g2d_pd: power-domain@10044100 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044100 0x20>;
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};
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msc_pd: power-domain@10044120 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044120 0x20>;
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};
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pinctrl_0: pinctrl@13400000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x13400000 0x1000>;
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interrupts = <0 45 0>;
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wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <0 32 0>;
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};
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};
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pinctrl_1: pinctrl@13410000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x13410000 0x1000>;
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interrupts = <0 78 0>;
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};
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pinctrl_2: pinctrl@14000000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x14000000 0x1000>;
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interrupts = <0 46 0>;
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};
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pinctrl_3: pinctrl@14010000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x14010000 0x1000>;
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interrupts = <0 50 0>;
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};
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pinctrl_4: pinctrl@03860000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x03860000 0x1000>;
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interrupts = <0 47 0>;
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};
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rtc@101E0000 {
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clocks = <&clock 317>;
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clock-names = "rtc";
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status = "okay";
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};
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amba {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,amba-bus";
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interrupt-parent = <&gic>;
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ranges;
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pdma0: pdma@121A0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x121A0000 0x1000>;
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interrupts = <0 34 0>;
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clocks = <&clock 362>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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};
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pdma1: pdma@121B0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x121B0000 0x1000>;
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interrupts = <0 35 0>;
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clocks = <&clock 363>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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};
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mdma0: mdma@10800000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x10800000 0x1000>;
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interrupts = <0 33 0>;
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clocks = <&clock 473>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <1>;
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};
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mdma1: mdma@11C10000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x11C10000 0x1000>;
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interrupts = <0 124 0>;
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clocks = <&clock 442>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <1>;
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};
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};
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spi_0: spi@12d20000 {
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compatible = "samsung,exynos4210-spi";
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reg = <0x12d20000 0x100>;
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interrupts = <0 66 0>;
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dmas = <&pdma0 5
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&pdma0 4>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_bus>;
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clocks = <&clock 271>, <&clock 135>;
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clock-names = "spi", "spi_busclk0";
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status = "disabled";
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};
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spi_1: spi@12d30000 {
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compatible = "samsung,exynos4210-spi";
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reg = <0x12d30000 0x100>;
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interrupts = <0 67 0>;
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dmas = <&pdma1 5
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&pdma1 4>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_bus>;
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clocks = <&clock 272>, <&clock 136>;
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clock-names = "spi", "spi_busclk0";
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status = "disabled";
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};
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spi_2: spi@12d40000 {
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compatible = "samsung,exynos4210-spi";
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reg = <0x12d40000 0x100>;
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interrupts = <0 68 0>;
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dmas = <&pdma0 7
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&pdma0 6>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi2_bus>;
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clocks = <&clock 273>, <&clock 137>;
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clock-names = "spi", "spi_busclk0";
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status = "disabled";
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};
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serial@12C00000 {
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clocks = <&clock 257>, <&clock 128>;
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clock-names = "uart", "clk_uart_baud0";
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};
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serial@12C10000 {
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clocks = <&clock 258>, <&clock 129>;
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clock-names = "uart", "clk_uart_baud0";
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};
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serial@12C20000 {
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clocks = <&clock 259>, <&clock 130>;
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clock-names = "uart", "clk_uart_baud0";
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};
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serial@12C30000 {
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clocks = <&clock 260>, <&clock 131>;
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clock-names = "uart", "clk_uart_baud0";
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};
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pwm: pwm@12dd0000 {
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compatible = "samsung,exynos4210-pwm";
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reg = <0x12dd0000 0x100>;
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samsung,pwm-outputs = <0>, <1>, <2>, <3>;
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#pwm-cells = <3>;
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clocks = <&clock 279>;
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clock-names = "timers";
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};
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dp_phy: video-phy@10040728 {
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compatible = "samsung,exynos5250-dp-video-phy";
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reg = <0x10040728 4>;
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#phy-cells = <0>;
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};
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dp-controller@145B0000 {
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clocks = <&clock 412>;
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clock-names = "dp";
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phys = <&dp_phy>;
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phy-names = "dp";
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};
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fimd@14400000 {
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samsung,power-domain = <&disp_pd>;
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clocks = <&clock 147>, <&clock 421>;
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clock-names = "sclk_fimd", "fimd";
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};
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adc: adc@12D10000 {
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compatible = "samsung,exynos-adc-v2";
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reg = <0x12D10000 0x100>, <0x10040720 0x4>;
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interrupts = <0 106 0>;
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clocks = <&clock 270>;
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clock-names = "adc";
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#io-channel-cells = <1>;
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io-channel-ranges;
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status = "disabled";
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};
|
|
|
|
i2c_0: i2c@12C60000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x12C60000 0x100>;
|
|
interrupts = <0 56 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock 261>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_1: i2c@12C70000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x12C70000 0x100>;
|
|
interrupts = <0 57 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock 262>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_2: i2c@12C80000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x12C80000 0x100>;
|
|
interrupts = <0 58 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock 263>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_3: i2c@12C90000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x12C90000 0x100>;
|
|
interrupts = <0 59 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock 264>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_4: i2c@12CA0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12CA0000 0x1000>;
|
|
interrupts = <0 60 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4_hs_bus>;
|
|
clocks = <&clock 265>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_5: i2c@12CB0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12CB0000 0x1000>;
|
|
interrupts = <0 61 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c5_hs_bus>;
|
|
clocks = <&clock 266>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_6: i2c@12CC0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12CC0000 0x1000>;
|
|
interrupts = <0 62 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c6_hs_bus>;
|
|
clocks = <&clock 267>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_7: i2c@12CD0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12CD0000 0x1000>;
|
|
interrupts = <0 63 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c7_hs_bus>;
|
|
clocks = <&clock 268>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_8: i2c@12E00000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12E00000 0x1000>;
|
|
interrupts = <0 87 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c8_hs_bus>;
|
|
clocks = <&clock 281>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_9: i2c@12E10000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12E10000 0x1000>;
|
|
interrupts = <0 88 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c9_hs_bus>;
|
|
clocks = <&clock 282>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_10: i2c@12E20000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12E20000 0x1000>;
|
|
interrupts = <0 203 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c10_hs_bus>;
|
|
clocks = <&clock 283>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hdmi@14530000 {
|
|
compatible = "samsung,exynos4212-hdmi";
|
|
reg = <0x14530000 0x70000>;
|
|
interrupts = <0 95 0>;
|
|
clocks = <&clock 413>, <&clock 143>, <&clock 768>,
|
|
<&clock 158>, <&clock 640>;
|
|
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
|
|
"sclk_hdmiphy", "mout_hdmi";
|
|
status = "disabled";
|
|
};
|
|
|
|
mixer@14450000 {
|
|
compatible = "samsung,exynos5420-mixer";
|
|
reg = <0x14450000 0x10000>;
|
|
interrupts = <0 94 0>;
|
|
clocks = <&clock 431>, <&clock 143>;
|
|
clock-names = "mixer", "sclk_hdmi";
|
|
};
|
|
|
|
gsc_0: video-scaler@13e00000 {
|
|
compatible = "samsung,exynos5-gsc";
|
|
reg = <0x13e00000 0x1000>;
|
|
interrupts = <0 85 0>;
|
|
clocks = <&clock 465>;
|
|
clock-names = "gscl";
|
|
samsung,power-domain = <&gsc_pd>;
|
|
};
|
|
|
|
gsc_1: video-scaler@13e10000 {
|
|
compatible = "samsung,exynos5-gsc";
|
|
reg = <0x13e10000 0x1000>;
|
|
interrupts = <0 86 0>;
|
|
clocks = <&clock 466>;
|
|
clock-names = "gscl";
|
|
samsung,power-domain = <&gsc_pd>;
|
|
};
|
|
|
|
tmu_cpu0: tmu@10060000 {
|
|
compatible = "samsung,exynos5420-tmu";
|
|
reg = <0x10060000 0x100>;
|
|
interrupts = <0 65 0>;
|
|
clocks = <&clock 318>;
|
|
clock-names = "tmu_apbif";
|
|
};
|
|
|
|
tmu_cpu1: tmu@10064000 {
|
|
compatible = "samsung,exynos5420-tmu";
|
|
reg = <0x10064000 0x100>;
|
|
interrupts = <0 183 0>;
|
|
clocks = <&clock 318>;
|
|
clock-names = "tmu_apbif";
|
|
};
|
|
|
|
tmu_cpu2: tmu@10068000 {
|
|
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
|
reg = <0x10068000 0x100>, <0x1006c000 0x4>;
|
|
interrupts = <0 184 0>;
|
|
clocks = <&clock 318>, <&clock 318>;
|
|
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
|
};
|
|
|
|
tmu_cpu3: tmu@1006c000 {
|
|
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
|
reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
|
|
interrupts = <0 185 0>;
|
|
clocks = <&clock 318>, <&clock 319>;
|
|
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
|
};
|
|
|
|
tmu_gpu: tmu@100a0000 {
|
|
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
|
reg = <0x100a0000 0x100>, <0x10068000 0x4>;
|
|
interrupts = <0 215 0>;
|
|
clocks = <&clock 319>, <&clock 318>;
|
|
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
|
};
|
|
};
|