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4729cbe038
cn78xx has a different interrupt architecture, so we have to manage the interrupts differently. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
41 lines
839 B
Plaintext
41 lines
839 B
Plaintext
* Two Wire Serial Interface (TWSI) / I2C
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- compatible: "cavium,octeon-3860-twsi"
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Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
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or
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compatible: "cavium,octeon-7890-twsi"
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Compatibility with cn78XX SOCs.
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- reg: The base address of the TWSI/I2C bus controller register bank.
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- #address-cells: Must be <1>.
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- #size-cells: Must be <0>. I2C addresses have no size component.
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- interrupts: A single interrupt specifier.
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- clock-frequency: The I2C bus clock rate in Hz.
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Example:
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twsi0: i2c@1180000001000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "cavium,octeon-3860-twsi";
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reg = <0x11800 0x00001000 0x0 0x200>;
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interrupts = <0 45>;
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clock-frequency = <100000>;
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rtc@68 {
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compatible = "dallas,ds1337";
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reg = <0x68>;
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};
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tmp@4c {
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compatible = "ti,tmp421";
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reg = <0x4c>;
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};
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};
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