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8d818c1055
Add CAAM driver that works using the DPSECI backend, i.e. manages
DPSECI DPAA2 objects sitting on the Management Complex (MC) fsl-mc bus.
Data transfers (crypto requests) are sent/received to/from CAAM crypto
engine via Queue Interface (v2), this being similar to existing caam/qi.
OTOH, configuration/setup (obtaining virtual queue IDs, authorization
etc.) is done by sending commands to the MC f/w.
Note that the CAAM accelerator included in DPAA2 platforms still has
Job Rings. However, the driver being added does not handle access
via this backend. Kconfig & Makefile are updated such that DPAA2-CAAM
(a.k.a. "caam/qi2") driver does not depend on caam/jr or caam/qi
backends - which rely on platform bus support (ctrl.c).
Support for the following aead and authenc algorithms is also added
in this patch:
-aead:
gcm(aes)
rfc4106(gcm(aes))
rfc4543(gcm(aes))
-authenc:
authenc(hmac({md5,sha*}),cbc({aes,des,des3_ede}))
echainiv(authenc(hmac({md5,sha*}),cbc({aes,des,des3_ede})))
authenc(hmac({md5,sha*}),rfc3686(ctr(aes))
seqiv(authenc(hmac({md5,sha*}),rfc3686(ctr(aes)))
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
50 lines
2.2 KiB
Makefile
50 lines
2.2 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_CRYPTO_DEV_ATMEL_AES) += atmel-aes.o
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obj-$(CONFIG_CRYPTO_DEV_ATMEL_SHA) += atmel-sha.o
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obj-$(CONFIG_CRYPTO_DEV_ATMEL_TDES) += atmel-tdes.o
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obj-$(CONFIG_CRYPTO_DEV_ATMEL_ECC) += atmel-ecc.o
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obj-$(CONFIG_CRYPTO_DEV_CAVIUM_ZIP) += cavium/
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obj-$(CONFIG_CRYPTO_DEV_CCP) += ccp/
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obj-$(CONFIG_CRYPTO_DEV_CCREE) += ccree/
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obj-$(CONFIG_CRYPTO_DEV_CHELSIO) += chelsio/
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obj-$(CONFIG_CRYPTO_DEV_CPT) += cavium/cpt/
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obj-$(CONFIG_CRYPTO_DEV_NITROX) += cavium/nitrox/
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obj-$(CONFIG_CRYPTO_DEV_EXYNOS_RNG) += exynos-rng.o
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obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON) += caam/
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obj-$(CONFIG_CRYPTO_DEV_GEODE) += geode-aes.o
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obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o
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obj-$(CONFIG_CRYPTO_DEV_IMGTEC_HASH) += img-hash.o
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obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o
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obj-$(CONFIG_CRYPTO_DEV_MARVELL_CESA) += marvell/
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obj-$(CONFIG_CRYPTO_DEV_MEDIATEK) += mediatek/
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obj-$(CONFIG_CRYPTO_DEV_MXS_DCP) += mxs-dcp.o
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obj-$(CONFIG_CRYPTO_DEV_MXC_SCC) += mxc-scc.o
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obj-$(CONFIG_CRYPTO_DEV_NIAGARA2) += n2_crypto.o
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n2_crypto-y := n2_core.o n2_asm.o
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obj-$(CONFIG_CRYPTO_DEV_NX) += nx/
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obj-$(CONFIG_CRYPTO_DEV_OMAP) += omap-crypto.o
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obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes-driver.o
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omap-aes-driver-objs := omap-aes.o omap-aes-gcm.o
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obj-$(CONFIG_CRYPTO_DEV_OMAP_DES) += omap-des.o
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obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o
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obj-$(CONFIG_CRYPTO_DEV_PADLOCK_AES) += padlock-aes.o
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obj-$(CONFIG_CRYPTO_DEV_PADLOCK_SHA) += padlock-sha.o
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obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o
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obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/
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obj-$(CONFIG_CRYPTO_DEV_QAT) += qat/
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obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
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obj-$(CONFIG_CRYPTO_DEV_QCOM_RNG) += qcom-rng.o
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obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/
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obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
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obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
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obj-$(CONFIG_ARCH_STM32) += stm32/
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obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/
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obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
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obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
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obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/
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obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
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obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
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obj-$(CONFIG_CRYPTO_DEV_SAFEXCEL) += inside-secure/
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obj-$(CONFIG_CRYPTO_DEV_ARTPEC6) += axis/
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obj-y += hisilicon/
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