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c7296700ed
Add definitions for IA64 GRU MMRs. Signed-off-by: Jack Steiner <steiner@sgi.com> Cc: "Luck, Tony" <tony.luck@intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
826 lines
36 KiB
C
826 lines
36 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* SGI UV MMR definitions
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*
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* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _ASM_IA64_UV_UV_MMRS_H
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#define _ASM_IA64_UV_UV_MMRS_H
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#define UV_MMR_ENABLE (1UL << 63)
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/* ========================================================================= */
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/* UVH_BAU_DATA_CONFIG */
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/* ========================================================================= */
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#define UVH_BAU_DATA_CONFIG 0x61680UL
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#define UVH_BAU_DATA_CONFIG_32 0x0438
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#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
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#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
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#define UVH_BAU_DATA_CONFIG_DM_SHFT 8
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#define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
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#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11
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#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
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#define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12
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#define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
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#define UVH_BAU_DATA_CONFIG_P_SHFT 13
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#define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
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#define UVH_BAU_DATA_CONFIG_T_SHFT 15
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#define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
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#define UVH_BAU_DATA_CONFIG_M_SHFT 16
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#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
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#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32
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#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
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union uvh_bau_data_config_u {
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unsigned long v;
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struct uvh_bau_data_config_s {
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unsigned long vector_ : 8; /* RW */
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unsigned long dm : 3; /* RW */
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unsigned long destmode : 1; /* RW */
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unsigned long status : 1; /* RO */
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unsigned long p : 1; /* RO */
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unsigned long rsvd_14 : 1; /* */
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unsigned long t : 1; /* RO */
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unsigned long m : 1; /* RW */
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unsigned long rsvd_17_31: 15; /* */
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unsigned long apic_id : 32; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_EVENT_OCCURRED0 */
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/* ========================================================================= */
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#define UVH_EVENT_OCCURRED0 0x70000UL
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#define UVH_EVENT_OCCURRED0_32 0x005e8
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#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0
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#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
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#define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
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#define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
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#define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
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#define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
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#define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3
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#define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
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#define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4
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#define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
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#define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5
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#define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
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#define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6
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#define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
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#define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
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#define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
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#define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
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#define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
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#define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
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#define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
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#define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
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#define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
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#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
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#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
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#define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
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#define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
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#define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
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#define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
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#define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
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#define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
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#define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
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#define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
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#define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
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#define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
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#define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
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#define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
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#define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
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#define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
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#define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
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#define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
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#define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
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#define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
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#define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
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#define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
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#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
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#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
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#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
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#define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
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#define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
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#define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
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#define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
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#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
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#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
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#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
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#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
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#define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43
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#define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
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#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
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#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
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#define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45
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#define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
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#define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
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#define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
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#define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
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#define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
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#define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
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#define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
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#define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
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#define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
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#define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
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#define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
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#define UVH_EVENT_OCCURRED0_RTC0_SHFT 51
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#define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
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#define UVH_EVENT_OCCURRED0_RTC1_SHFT 52
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#define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
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#define UVH_EVENT_OCCURRED0_RTC2_SHFT 53
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#define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
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#define UVH_EVENT_OCCURRED0_RTC3_SHFT 54
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#define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
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#define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55
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#define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
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#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
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#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
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union uvh_event_occurred0_u {
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unsigned long v;
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struct uvh_event_occurred0_s {
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unsigned long lb_hcerr : 1; /* RW, W1C */
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unsigned long gr0_hcerr : 1; /* RW, W1C */
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unsigned long gr1_hcerr : 1; /* RW, W1C */
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unsigned long lh_hcerr : 1; /* RW, W1C */
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unsigned long rh_hcerr : 1; /* RW, W1C */
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unsigned long xn_hcerr : 1; /* RW, W1C */
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unsigned long si_hcerr : 1; /* RW, W1C */
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unsigned long lb_aoerr0 : 1; /* RW, W1C */
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unsigned long gr0_aoerr0 : 1; /* RW, W1C */
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unsigned long gr1_aoerr0 : 1; /* RW, W1C */
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unsigned long lh_aoerr0 : 1; /* RW, W1C */
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unsigned long rh_aoerr0 : 1; /* RW, W1C */
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unsigned long xn_aoerr0 : 1; /* RW, W1C */
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unsigned long si_aoerr0 : 1; /* RW, W1C */
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unsigned long lb_aoerr1 : 1; /* RW, W1C */
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unsigned long gr0_aoerr1 : 1; /* RW, W1C */
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unsigned long gr1_aoerr1 : 1; /* RW, W1C */
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unsigned long lh_aoerr1 : 1; /* RW, W1C */
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unsigned long rh_aoerr1 : 1; /* RW, W1C */
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unsigned long xn_aoerr1 : 1; /* RW, W1C */
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unsigned long si_aoerr1 : 1; /* RW, W1C */
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unsigned long rh_vpi_int : 1; /* RW, W1C */
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unsigned long system_shutdown_int : 1; /* RW, W1C */
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unsigned long lb_irq_int_0 : 1; /* RW, W1C */
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unsigned long lb_irq_int_1 : 1; /* RW, W1C */
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unsigned long lb_irq_int_2 : 1; /* RW, W1C */
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unsigned long lb_irq_int_3 : 1; /* RW, W1C */
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unsigned long lb_irq_int_4 : 1; /* RW, W1C */
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unsigned long lb_irq_int_5 : 1; /* RW, W1C */
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unsigned long lb_irq_int_6 : 1; /* RW, W1C */
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unsigned long lb_irq_int_7 : 1; /* RW, W1C */
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unsigned long lb_irq_int_8 : 1; /* RW, W1C */
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unsigned long lb_irq_int_9 : 1; /* RW, W1C */
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unsigned long lb_irq_int_10 : 1; /* RW, W1C */
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unsigned long lb_irq_int_11 : 1; /* RW, W1C */
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unsigned long lb_irq_int_12 : 1; /* RW, W1C */
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unsigned long lb_irq_int_13 : 1; /* RW, W1C */
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unsigned long lb_irq_int_14 : 1; /* RW, W1C */
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unsigned long lb_irq_int_15 : 1; /* RW, W1C */
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unsigned long l1_nmi_int : 1; /* RW, W1C */
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unsigned long stop_clock : 1; /* RW, W1C */
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unsigned long asic_to_l1 : 1; /* RW, W1C */
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unsigned long l1_to_asic : 1; /* RW, W1C */
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unsigned long ltc_int : 1; /* RW, W1C */
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unsigned long la_seq_trigger : 1; /* RW, W1C */
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unsigned long ipi_int : 1; /* RW, W1C */
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unsigned long extio_int0 : 1; /* RW, W1C */
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unsigned long extio_int1 : 1; /* RW, W1C */
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unsigned long extio_int2 : 1; /* RW, W1C */
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unsigned long extio_int3 : 1; /* RW, W1C */
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unsigned long profile_int : 1; /* RW, W1C */
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unsigned long rtc0 : 1; /* RW, W1C */
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unsigned long rtc1 : 1; /* RW, W1C */
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unsigned long rtc2 : 1; /* RW, W1C */
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unsigned long rtc3 : 1; /* RW, W1C */
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unsigned long bau_data : 1; /* RW, W1C */
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unsigned long power_management_req : 1; /* RW, W1C */
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unsigned long rsvd_57_63 : 7; /* */
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} s;
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};
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/* ========================================================================= */
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/* UVH_EVENT_OCCURRED0_ALIAS */
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/* ========================================================================= */
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#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
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#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0
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/* ========================================================================= */
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/* UVH_GR0_TLB_INT0_CONFIG */
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/* ========================================================================= */
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#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
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#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
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#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
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#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8
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#define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
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#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
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#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
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#define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
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#define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
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#define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13
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#define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
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#define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15
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#define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
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#define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16
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#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
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#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
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#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
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union uvh_gr0_tlb_int0_config_u {
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unsigned long v;
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struct uvh_gr0_tlb_int0_config_s {
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unsigned long vector_ : 8; /* RW */
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unsigned long dm : 3; /* RW */
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unsigned long destmode : 1; /* RW */
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unsigned long status : 1; /* RO */
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unsigned long p : 1; /* RO */
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unsigned long rsvd_14 : 1; /* */
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unsigned long t : 1; /* RO */
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unsigned long m : 1; /* RW */
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unsigned long rsvd_17_31: 15; /* */
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unsigned long apic_id : 32; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_GR0_TLB_INT1_CONFIG */
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/* ========================================================================= */
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#define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
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#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
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#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
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#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8
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#define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
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#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11
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#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
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#define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12
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#define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
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#define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13
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#define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
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#define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15
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#define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
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#define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16
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#define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
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#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32
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#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
|
|
|
|
union uvh_gr0_tlb_int1_config_u {
|
|
unsigned long v;
|
|
struct uvh_gr0_tlb_int1_config_s {
|
|
unsigned long vector_ : 8; /* RW */
|
|
unsigned long dm : 3; /* RW */
|
|
unsigned long destmode : 1; /* RW */
|
|
unsigned long status : 1; /* RO */
|
|
unsigned long p : 1; /* RO */
|
|
unsigned long rsvd_14 : 1; /* */
|
|
unsigned long t : 1; /* RO */
|
|
unsigned long m : 1; /* RW */
|
|
unsigned long rsvd_17_31: 15; /* */
|
|
unsigned long apic_id : 32; /* RW */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_GR1_TLB_INT0_CONFIG */
|
|
/* ========================================================================= */
|
|
#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL
|
|
|
|
#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
|
|
#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
|
|
#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8
|
|
#define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
|
|
#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11
|
|
#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
|
|
#define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12
|
|
#define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
|
|
#define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13
|
|
#define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
|
|
#define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15
|
|
#define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
|
|
#define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16
|
|
#define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
|
|
#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32
|
|
#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
|
|
|
|
union uvh_gr1_tlb_int0_config_u {
|
|
unsigned long v;
|
|
struct uvh_gr1_tlb_int0_config_s {
|
|
unsigned long vector_ : 8; /* RW */
|
|
unsigned long dm : 3; /* RW */
|
|
unsigned long destmode : 1; /* RW */
|
|
unsigned long status : 1; /* RO */
|
|
unsigned long p : 1; /* RO */
|
|
unsigned long rsvd_14 : 1; /* */
|
|
unsigned long t : 1; /* RO */
|
|
unsigned long m : 1; /* RW */
|
|
unsigned long rsvd_17_31: 15; /* */
|
|
unsigned long apic_id : 32; /* RW */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_GR1_TLB_INT1_CONFIG */
|
|
/* ========================================================================= */
|
|
#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL
|
|
|
|
#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
|
|
#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
|
|
#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8
|
|
#define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
|
|
#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11
|
|
#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
|
|
#define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12
|
|
#define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
|
|
#define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13
|
|
#define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
|
|
#define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15
|
|
#define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
|
|
#define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16
|
|
#define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
|
|
#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32
|
|
#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
|
|
|
|
union uvh_gr1_tlb_int1_config_u {
|
|
unsigned long v;
|
|
struct uvh_gr1_tlb_int1_config_s {
|
|
unsigned long vector_ : 8; /* RW */
|
|
unsigned long dm : 3; /* RW */
|
|
unsigned long destmode : 1; /* RW */
|
|
unsigned long status : 1; /* RO */
|
|
unsigned long p : 1; /* RO */
|
|
unsigned long rsvd_14 : 1; /* */
|
|
unsigned long t : 1; /* RO */
|
|
unsigned long m : 1; /* RW */
|
|
unsigned long rsvd_17_31: 15; /* */
|
|
unsigned long apic_id : 32; /* RW */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_INT_CMPB */
|
|
/* ========================================================================= */
|
|
#define UVH_INT_CMPB 0x22080UL
|
|
|
|
#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
|
|
#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
|
|
|
|
union uvh_int_cmpb_u {
|
|
unsigned long v;
|
|
struct uvh_int_cmpb_s {
|
|
unsigned long real_time_cmpb : 56; /* RW */
|
|
unsigned long rsvd_56_63 : 8; /* */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_INT_CMPC */
|
|
/* ========================================================================= */
|
|
#define UVH_INT_CMPC 0x22100UL
|
|
|
|
#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
|
|
#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL
|
|
|
|
union uvh_int_cmpc_u {
|
|
unsigned long v;
|
|
struct uvh_int_cmpc_s {
|
|
unsigned long real_time_cmpc : 56; /* RW */
|
|
unsigned long rsvd_56_63 : 8; /* */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_INT_CMPD */
|
|
/* ========================================================================= */
|
|
#define UVH_INT_CMPD 0x22180UL
|
|
|
|
#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
|
|
#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL
|
|
|
|
union uvh_int_cmpd_u {
|
|
unsigned long v;
|
|
struct uvh_int_cmpd_s {
|
|
unsigned long real_time_cmpd : 56; /* RW */
|
|
unsigned long rsvd_56_63 : 8; /* */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_NODE_ID */
|
|
/* ========================================================================= */
|
|
#define UVH_NODE_ID 0x0UL
|
|
|
|
#define UVH_NODE_ID_FORCE1_SHFT 0
|
|
#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
|
|
#define UVH_NODE_ID_MANUFACTURER_SHFT 1
|
|
#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
|
|
#define UVH_NODE_ID_PART_NUMBER_SHFT 12
|
|
#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
|
|
#define UVH_NODE_ID_REVISION_SHFT 28
|
|
#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
|
|
#define UVH_NODE_ID_NODE_ID_SHFT 32
|
|
#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
|
|
#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48
|
|
#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
|
|
#define UVH_NODE_ID_NI_PORT_SHFT 56
|
|
#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
|
|
|
|
union uvh_node_id_u {
|
|
unsigned long v;
|
|
struct uvh_node_id_s {
|
|
unsigned long force1 : 1; /* RO */
|
|
unsigned long manufacturer : 11; /* RO */
|
|
unsigned long part_number : 16; /* RO */
|
|
unsigned long revision : 4; /* RO */
|
|
unsigned long node_id : 15; /* RW */
|
|
unsigned long rsvd_47 : 1; /* */
|
|
unsigned long nodes_per_bit : 7; /* RW */
|
|
unsigned long rsvd_55 : 1; /* */
|
|
unsigned long ni_port : 4; /* RO */
|
|
unsigned long rsvd_60_63 : 4; /* */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
|
|
/* ========================================================================= */
|
|
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
|
|
|
|
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
|
|
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
|
|
|
|
union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
|
|
unsigned long v;
|
|
struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
|
|
unsigned long rsvd_0_23 : 24; /* */
|
|
unsigned long dest_base : 22; /* RW */
|
|
unsigned long rsvd_46_63: 18; /* */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */
|
|
/* ========================================================================= */
|
|
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
|
|
|
|
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
|
|
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
|
|
|
|
union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
|
|
unsigned long v;
|
|
struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
|
|
unsigned long rsvd_0_23 : 24; /* */
|
|
unsigned long dest_base : 22; /* RW */
|
|
unsigned long rsvd_46_63: 18; /* */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */
|
|
/* ========================================================================= */
|
|
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
|
|
|
|
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
|
|
#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
|
|
|
|
union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
|
|
unsigned long v;
|
|
struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
|
|
unsigned long rsvd_0_23 : 24; /* */
|
|
unsigned long dest_base : 22; /* RW */
|
|
unsigned long rsvd_46_63: 18; /* */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
|
|
/* ========================================================================= */
|
|
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
|
|
|
|
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
|
|
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
|
|
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
|
|
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
|
|
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
|
|
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
|
|
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
|
|
#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
|
|
|
|
union uvh_rh_gam_gru_overlay_config_mmr_u {
|
|
unsigned long v;
|
|
struct uvh_rh_gam_gru_overlay_config_mmr_s {
|
|
unsigned long rsvd_0_27: 28; /* */
|
|
unsigned long base : 18; /* RW */
|
|
unsigned long rsvd_46_47: 2; /* */
|
|
unsigned long gr4 : 1; /* RW */
|
|
unsigned long rsvd_49_51: 3; /* */
|
|
unsigned long n_gru : 4; /* RW */
|
|
unsigned long rsvd_56_62: 7; /* */
|
|
unsigned long enable : 1; /* RW */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
|
|
/* ========================================================================= */
|
|
#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
|
|
|
|
#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
|
|
#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
|
|
#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
|
|
#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
|
|
#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
|
|
#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
|
|
|
|
union uvh_rh_gam_mmr_overlay_config_mmr_u {
|
|
unsigned long v;
|
|
struct uvh_rh_gam_mmr_overlay_config_mmr_s {
|
|
unsigned long rsvd_0_25: 26; /* */
|
|
unsigned long base : 20; /* RW */
|
|
unsigned long dual_hub : 1; /* RW */
|
|
unsigned long rsvd_47_62: 16; /* */
|
|
unsigned long enable : 1; /* RW */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_RTC */
|
|
/* ========================================================================= */
|
|
#define UVH_RTC 0x340000UL
|
|
|
|
#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
|
|
#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
|
|
|
|
union uvh_rtc_u {
|
|
unsigned long v;
|
|
struct uvh_rtc_s {
|
|
unsigned long real_time_clock : 56; /* RW */
|
|
unsigned long rsvd_56_63 : 8; /* */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_RTC1_INT_CONFIG */
|
|
/* ========================================================================= */
|
|
#define UVH_RTC1_INT_CONFIG 0x615c0UL
|
|
|
|
#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0
|
|
#define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
|
|
#define UVH_RTC1_INT_CONFIG_DM_SHFT 8
|
|
#define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
|
|
#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11
|
|
#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
|
|
#define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12
|
|
#define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
|
|
#define UVH_RTC1_INT_CONFIG_P_SHFT 13
|
|
#define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
|
|
#define UVH_RTC1_INT_CONFIG_T_SHFT 15
|
|
#define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
|
|
#define UVH_RTC1_INT_CONFIG_M_SHFT 16
|
|
#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
|
|
#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32
|
|
#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
|
|
|
|
union uvh_rtc1_int_config_u {
|
|
unsigned long v;
|
|
struct uvh_rtc1_int_config_s {
|
|
unsigned long vector_ : 8; /* RW */
|
|
unsigned long dm : 3; /* RW */
|
|
unsigned long destmode : 1; /* RW */
|
|
unsigned long status : 1; /* RO */
|
|
unsigned long p : 1; /* RO */
|
|
unsigned long rsvd_14 : 1; /* */
|
|
unsigned long t : 1; /* RO */
|
|
unsigned long m : 1; /* RW */
|
|
unsigned long rsvd_17_31: 15; /* */
|
|
unsigned long apic_id : 32; /* RW */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_RTC2_INT_CONFIG */
|
|
/* ========================================================================= */
|
|
#define UVH_RTC2_INT_CONFIG 0x61600UL
|
|
|
|
#define UVH_RTC2_INT_CONFIG_VECTOR_SHFT 0
|
|
#define UVH_RTC2_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
|
|
#define UVH_RTC2_INT_CONFIG_DM_SHFT 8
|
|
#define UVH_RTC2_INT_CONFIG_DM_MASK 0x0000000000000700UL
|
|
#define UVH_RTC2_INT_CONFIG_DESTMODE_SHFT 11
|
|
#define UVH_RTC2_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
|
|
#define UVH_RTC2_INT_CONFIG_STATUS_SHFT 12
|
|
#define UVH_RTC2_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
|
|
#define UVH_RTC2_INT_CONFIG_P_SHFT 13
|
|
#define UVH_RTC2_INT_CONFIG_P_MASK 0x0000000000002000UL
|
|
#define UVH_RTC2_INT_CONFIG_T_SHFT 15
|
|
#define UVH_RTC2_INT_CONFIG_T_MASK 0x0000000000008000UL
|
|
#define UVH_RTC2_INT_CONFIG_M_SHFT 16
|
|
#define UVH_RTC2_INT_CONFIG_M_MASK 0x0000000000010000UL
|
|
#define UVH_RTC2_INT_CONFIG_APIC_ID_SHFT 32
|
|
#define UVH_RTC2_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
|
|
|
|
union uvh_rtc2_int_config_u {
|
|
unsigned long v;
|
|
struct uvh_rtc2_int_config_s {
|
|
unsigned long vector_ : 8; /* RW */
|
|
unsigned long dm : 3; /* RW */
|
|
unsigned long destmode : 1; /* RW */
|
|
unsigned long status : 1; /* RO */
|
|
unsigned long p : 1; /* RO */
|
|
unsigned long rsvd_14 : 1; /* */
|
|
unsigned long t : 1; /* RO */
|
|
unsigned long m : 1; /* RW */
|
|
unsigned long rsvd_17_31: 15; /* */
|
|
unsigned long apic_id : 32; /* RW */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_RTC3_INT_CONFIG */
|
|
/* ========================================================================= */
|
|
#define UVH_RTC3_INT_CONFIG 0x61640UL
|
|
|
|
#define UVH_RTC3_INT_CONFIG_VECTOR_SHFT 0
|
|
#define UVH_RTC3_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
|
|
#define UVH_RTC3_INT_CONFIG_DM_SHFT 8
|
|
#define UVH_RTC3_INT_CONFIG_DM_MASK 0x0000000000000700UL
|
|
#define UVH_RTC3_INT_CONFIG_DESTMODE_SHFT 11
|
|
#define UVH_RTC3_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
|
|
#define UVH_RTC3_INT_CONFIG_STATUS_SHFT 12
|
|
#define UVH_RTC3_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
|
|
#define UVH_RTC3_INT_CONFIG_P_SHFT 13
|
|
#define UVH_RTC3_INT_CONFIG_P_MASK 0x0000000000002000UL
|
|
#define UVH_RTC3_INT_CONFIG_T_SHFT 15
|
|
#define UVH_RTC3_INT_CONFIG_T_MASK 0x0000000000008000UL
|
|
#define UVH_RTC3_INT_CONFIG_M_SHFT 16
|
|
#define UVH_RTC3_INT_CONFIG_M_MASK 0x0000000000010000UL
|
|
#define UVH_RTC3_INT_CONFIG_APIC_ID_SHFT 32
|
|
#define UVH_RTC3_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
|
|
|
|
union uvh_rtc3_int_config_u {
|
|
unsigned long v;
|
|
struct uvh_rtc3_int_config_s {
|
|
unsigned long vector_ : 8; /* RW */
|
|
unsigned long dm : 3; /* RW */
|
|
unsigned long destmode : 1; /* RW */
|
|
unsigned long status : 1; /* RO */
|
|
unsigned long p : 1; /* RO */
|
|
unsigned long rsvd_14 : 1; /* */
|
|
unsigned long t : 1; /* RO */
|
|
unsigned long m : 1; /* RW */
|
|
unsigned long rsvd_17_31: 15; /* */
|
|
unsigned long apic_id : 32; /* RW */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_RTC_INC_RATIO */
|
|
/* ========================================================================= */
|
|
#define UVH_RTC_INC_RATIO 0x350000UL
|
|
|
|
#define UVH_RTC_INC_RATIO_FRACTION_SHFT 0
|
|
#define UVH_RTC_INC_RATIO_FRACTION_MASK 0x00000000000fffffUL
|
|
#define UVH_RTC_INC_RATIO_RATIO_SHFT 20
|
|
#define UVH_RTC_INC_RATIO_RATIO_MASK 0x0000000000700000UL
|
|
|
|
union uvh_rtc_inc_ratio_u {
|
|
unsigned long v;
|
|
struct uvh_rtc_inc_ratio_s {
|
|
unsigned long fraction : 20; /* RW */
|
|
unsigned long ratio : 3; /* RW */
|
|
unsigned long rsvd_23_63: 41; /* */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_SI_ADDR_MAP_CONFIG */
|
|
/* ========================================================================= */
|
|
#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
|
|
|
|
#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
|
|
#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
|
|
#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
|
|
#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
|
|
|
|
union uvh_si_addr_map_config_u {
|
|
unsigned long v;
|
|
struct uvh_si_addr_map_config_s {
|
|
unsigned long m_skt : 6; /* RW */
|
|
unsigned long rsvd_6_7: 2; /* */
|
|
unsigned long n_skt : 4; /* RW */
|
|
unsigned long rsvd_12_63: 52; /* */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_SI_ALIAS0_OVERLAY_CONFIG */
|
|
/* ========================================================================= */
|
|
#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
|
|
|
|
#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
|
|
#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
|
|
#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
|
|
#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
|
|
#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
|
|
#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
|
|
|
|
union uvh_si_alias0_overlay_config_u {
|
|
unsigned long v;
|
|
struct uvh_si_alias0_overlay_config_s {
|
|
unsigned long rsvd_0_23: 24; /* */
|
|
unsigned long base : 8; /* RW */
|
|
unsigned long rsvd_32_47: 16; /* */
|
|
unsigned long m_alias : 5; /* RW */
|
|
unsigned long rsvd_53_62: 10; /* */
|
|
unsigned long enable : 1; /* RW */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_SI_ALIAS1_OVERLAY_CONFIG */
|
|
/* ========================================================================= */
|
|
#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
|
|
|
|
#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
|
|
#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
|
|
#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
|
|
#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
|
|
#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
|
|
#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
|
|
|
|
union uvh_si_alias1_overlay_config_u {
|
|
unsigned long v;
|
|
struct uvh_si_alias1_overlay_config_s {
|
|
unsigned long rsvd_0_23: 24; /* */
|
|
unsigned long base : 8; /* RW */
|
|
unsigned long rsvd_32_47: 16; /* */
|
|
unsigned long m_alias : 5; /* RW */
|
|
unsigned long rsvd_53_62: 10; /* */
|
|
unsigned long enable : 1; /* RW */
|
|
} s;
|
|
};
|
|
|
|
/* ========================================================================= */
|
|
/* UVH_SI_ALIAS2_OVERLAY_CONFIG */
|
|
/* ========================================================================= */
|
|
#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
|
|
|
|
#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
|
|
#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
|
|
#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
|
|
#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
|
|
#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
|
|
#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
|
|
|
|
union uvh_si_alias2_overlay_config_u {
|
|
unsigned long v;
|
|
struct uvh_si_alias2_overlay_config_s {
|
|
unsigned long rsvd_0_23: 24; /* */
|
|
unsigned long base : 8; /* RW */
|
|
unsigned long rsvd_32_47: 16; /* */
|
|
unsigned long m_alias : 5; /* RW */
|
|
unsigned long rsvd_53_62: 10; /* */
|
|
unsigned long enable : 1; /* RW */
|
|
} s;
|
|
};
|
|
|
|
|
|
#endif /* _ASM_IA64_UV_UV_MMRS_H */
|