Mostafa Saleh dcf89d1111 KVM: arm64: Add missing BTI instructions ... Some bti instructions were missing from commit b53d4a2723 ("KVM: arm64: Use BTI for nvhe") 1) kvm_host_psci_cpu_entry kvm_host_psci_cpu_entry is called from __kvm_hyp_init_cpu through "br" instruction as __kvm_hyp_init_cpu resides in idmap section while kvm_host_psci_cpu_entry is in hyp .text so the offset is larger than 128MB range covered by "b". Which means that this function should start with "bti j" instruction. LLVM which is the only compiler supporting BTI for Linux, adds "bti j" for jump tables or by when taking the address of the block [1]. Same behaviour is observed with GCC. As kvm_host_psci_cpu_entry is a C function, this must be done in assembly. Another solution is to use X16/X17 with "br", as according to ARM ARM DDI0487I.a RLJHCL/IGMGRS, PACIASP has an implicit branch target identification instruction that is compatible with PSTATE.BTYPE 0b01 which includes "br X16/X17" And the kvm_host_psci_cpu_entry has PACIASP as it is an external function. Although, using explicit "bti" makes it more clear than relying on which register is used. A third solution is to clear SCTLR_EL2.BT, which would make PACIASP compatible PSTATE.BTYPE 0b11 ("br" to other registers). However this deviates from the kernel behaviour (in bti_enable()). 2) Spectre vector table "br" instructions are generated at runtime for the vector table (__bp_harden_hyp_vecs). These branches would land on vectors in __kvm_hyp_vector at offset 8. As all the macros are defined with valid_vect/invalid_vect, it is sufficient to add "bti j" at the correct offset. [1] https://reviews.llvm.org/D52867 Fixes: b53d4a2723 ("KVM: arm64: Use BTI for nvhe") Signed-off-by: Mostafa Saleh <smostafa@google.com> Reported-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Marc Zyngier <maz@kernel.org> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Link: https://lore.kernel.org/r/20230706152240.685684-1-smostafa@google.com Signed-off-by: Oliver Upton <oliver.upton@linux.dev>		2023-07-12 22:15:36 +00:00
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include	ARM64:	2023-07-03 15:32:22 -07:00
nvhe	KVM: arm64: Add missing BTI instructions	2023-07-12 22:15:36 +00:00
vhe	KVM/arm64 updates for 6.5	2023-07-01 07:04:29 -04:00
aarch32.c	KVM: arm64: Move kvm_vcpu_trap_il_is32bit into kvm_skip_instr32()	2020-11-10 08:34:24 +00:00
entry.S	KVM: arm64: Use symbolic definition for ISR_EL1.A	2023-01-12 16:31:33 +00:00
exception.c	KVM: arm64: nv: Support virtual EL2 exceptions	2023-02-11 09:16:11 +00:00
fpsimd.S	KVM: arm64: Remove unused __sve_save_state	2021-11-22 16:01:39 +00:00
hyp-constants.c	KVM: arm64: Instantiate pKVM hypervisor VM and vCPU structures from EL1	2022-11-11 17:16:24 +00:00
hyp-entry.S	KVM: arm64: Add missing BTI instructions	2023-07-12 22:15:36 +00:00
Makefile	KVM: arm64: Enable stack protection and branch profiling for VHE	2022-10-09 03:15:55 +01:00
pgtable.c	KVM: arm64: Correctly handle page aging notifiers for unaligned memslot	2023-07-12 20:10:40 +00:00
vgic-v2-cpuif-proxy.c	KVM: arm64: Remove hyp_symbol_addr	2021-01-23 14:01:00 +00:00
vgic-v3-sr.c	KVM: arm64: Treat ESR_EL2 as a 64-bit register	2022-04-29 19:26:27 +01:00