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444fe99135
This tag contains an assortment of RISC-V-related fixups that we found after rc4. They're all really unrelated: * The addition of a 32-bit defconfig, to emphasize testing the 32-bit port. * A device tree bindings patch, which is pre-work for some patches that target 5.2. * A fix to support booting on systems with more physical memory than the maximum supported by the kernel. These work for me when merged into Linus' master from this morning, which has no conflicts. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEAM520YNJYN/OiG3470yhUCzLq0EFAly1A3QTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRDvTKFQLMurQQeID/44J6cdMqiSik5HrLKncOQk47a+Df1F y9elqrbWc/c2mClIjxg4uRNyQdwlea2p3ymFN5cymk7d8vxLi/S9jZTZDuJgk6SV oLubn7O3FXvrs9++wsYC+68XnqLgiym35stJslmmnMK6auttD37lXu/XOSJlZ3Zg k7HUd7s1yn6NR531313nto4tNxSShn4aZLT3o0FxZSplmgnEXXNonbaGbvGlFZFU CWz76UvcoxTSc/OmhtRk9z2cjlhJaxshq+iPXSOVPBSkQ17h9tDlFAE+OVqGwcV9 Ar0at/567wA8Ejx2ZUduDVsGjR9fgJa3TYIMzyABYwZ/9BnRuNFawg9jXwSd7T5s tBEkNioGWM9zFOGpDXuktayhMORdDJRbfOkqOuN6LSvrObqkNlSeKfiNwSQvuffx zI7SzTluzRHUasndxkEAAm3eIAA4FMwfuehXICWNiffq8w06aLIomT0oOBz7A3dx SvIN1NiWVAC1cVpKUsXtSY0ytURel2nOPKNvIIkpgvczezbOJ17NLPPOQY1V/PWK 1h22huhto9BwgJtadf4ubf/AfFO7/JUG8rHG8QixZHJXNYx2Jbv5o2dng3TzKyf6 TeWu2kZnuNT/OINhEjsFouXHB/UcH5RHruPL+T0LcUUbyNRTJxtuxn8QMuVElUlq fyQNi7mmEAEJYg== =LL9T -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-5.1-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux Pull RISC-V fixes from Palmer Dabbelt: "This contains an assortment of RISC-V-related fixups that we found after rc4. They're all really unrelated: - The addition of a 32-bit defconfig, to emphasize testing the 32-bit port. - A device tree bindings patch, which is pre-work for some patches that target 5.2. - A fix to support booting on systems with more physical memory than the maximum supported by the kernel" * tag 'riscv-for-linus-5.1-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux: RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systems dt-bindings: clock: sifive: add FU540-C000 PRCI clock constants RISC-V: Add separate defconfig for 32bit systems |
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