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5a2394534b
The m68k core irq code stopped honoring these flags during the irq restructuring in 2006. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
79 lines
1.9 KiB
C
79 lines
1.9 KiB
C
/*
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* linux/arch/m68k/hp300/time.c
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*
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* Copyright (C) 1998 Philip Blundell <philb@gnu.org>
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*
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* This file contains the HP300-specific time handling code.
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*/
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#include <asm/ptrace.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/kernel_stat.h>
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#include <linux/interrupt.h>
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#include <asm/machdep.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/traps.h>
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#include <asm/blinken.h>
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/* Clock hardware definitions */
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#define CLOCKBASE 0xf05f8000
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#define CLKCR1 0x1
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#define CLKCR2 0x3
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#define CLKCR3 CLKCR1
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#define CLKSR CLKCR2
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#define CLKMSB1 0x5
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#define CLKMSB2 0x9
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#define CLKMSB3 0xD
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/* This is for machines which generate the exact clock. */
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#define USECS_PER_JIFFY (1000000/HZ)
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#define INTVAL ((10000 / 4) - 1)
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static irqreturn_t hp300_tick(int irq, void *dev_id)
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{
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unsigned long tmp;
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irq_handler_t vector = dev_id;
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in_8(CLOCKBASE + CLKSR);
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asm volatile ("movpw %1@(5),%0" : "=d" (tmp) : "a" (CLOCKBASE));
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/* Turn off the network and SCSI leds */
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blinken_leds(0, 0xe0);
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return vector(irq, NULL);
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}
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unsigned long hp300_gettimeoffset(void)
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{
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/* Read current timer 1 value */
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unsigned char lsb, msb1, msb2;
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unsigned short ticks;
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msb1 = in_8(CLOCKBASE + 5);
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lsb = in_8(CLOCKBASE + 7);
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msb2 = in_8(CLOCKBASE + 5);
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if (msb1 != msb2)
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/* A carry happened while we were reading. Read it again */
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lsb = in_8(CLOCKBASE + 7);
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ticks = INTVAL - ((msb2 << 8) | lsb);
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return (USECS_PER_JIFFY * ticks) / INTVAL;
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}
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void __init hp300_sched_init(irq_handler_t vector)
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{
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out_8(CLOCKBASE + CLKCR2, 0x1); /* select CR1 */
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out_8(CLOCKBASE + CLKCR1, 0x1); /* reset */
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asm volatile(" movpw %0,%1@(5)" : : "d" (INTVAL), "a" (CLOCKBASE));
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if (request_irq(IRQ_AUTO_6, hp300_tick, 0, "timer tick", vector))
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pr_err("Couldn't register timer interrupt\n");
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out_8(CLOCKBASE + CLKCR2, 0x1); /* select CR1 */
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out_8(CLOCKBASE + CLKCR1, 0x40); /* enable irq */
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}
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