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b2a3c5be4d
It is still necessary to handle icache coherency in flush_cache_range() and copy_to_user_page() when the icache fills from the dcache, even though the dcache does not need to be written back. However when this handling was added in commit2eaa7ec286
("[MIPS] Handle I-cache coherency in flush_cache_range()"), it did not do any icache flushing when it fills from dcache. Therefore fix r4k_flush_cache_range() to run local_r4k_flush_cache_range() without taking into account whether icache fills from dcache, so that the icache coherency gets handled. Checks are also added in local_r4k_flush_cache_range() so that the dcache blast doesn't take place when icache fills from dcache. A test to mmap a page PROT_READ|PROT_WRITE, modify code in it, and mprotect it to VM_READ|VM_EXEC (similar to case described in above commit) can hit this case quite easily to verify the fix. A similar check was added in commitf8829caee3
("[MIPS] Fix aliasing bug in copy_to_user_page / copy_from_user_page"), so also fix copy_to_user_page() similarly, to call flush_cache_page() without taking into account whether icache fills from dcache, since flush_cache_page() already takes that into account to avoid performing a dcache flush. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12179/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
537 lines
13 KiB
C
537 lines
13 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 - 2000 Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/bug.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/pagemap.h>
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#include <linux/ptrace.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/bootmem.h>
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#include <linux/highmem.h>
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#include <linux/swap.h>
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#include <linux/proc_fs.h>
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#include <linux/pfn.h>
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#include <linux/hardirq.h>
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#include <linux/gfp.h>
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#include <linux/kcore.h>
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#include <asm/asm-offsets.h>
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#include <asm/bootinfo.h>
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#include <asm/cachectl.h>
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#include <asm/cpu.h>
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#include <asm/dma.h>
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#include <asm/kmap_types.h>
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#include <asm/maar.h>
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#include <asm/mmu_context.h>
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#include <asm/sections.h>
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#include <asm/pgtable.h>
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#include <asm/pgalloc.h>
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#include <asm/tlb.h>
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#include <asm/fixmap.h>
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#include <asm/maar.h>
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/*
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* We have up to 8 empty zeroed pages so we can map one of the right colour
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* when needed. This is necessary only on R4000 / R4400 SC and MC versions
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* where we have to avoid VCED / VECI exceptions for good performance at
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* any price. Since page is never written to after the initialization we
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* don't have to care about aliases on other CPUs.
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*/
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unsigned long empty_zero_page, zero_page_mask;
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EXPORT_SYMBOL_GPL(empty_zero_page);
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EXPORT_SYMBOL(zero_page_mask);
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/*
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* Not static inline because used by IP27 special magic initialization code
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*/
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void setup_zero_pages(void)
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{
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unsigned int order, i;
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struct page *page;
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if (cpu_has_vce)
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order = 3;
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else
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order = 0;
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empty_zero_page = __get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
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if (!empty_zero_page)
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panic("Oh boy, that early out of memory?");
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page = virt_to_page((void *)empty_zero_page);
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split_page(page, order);
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for (i = 0; i < (1 << order); i++, page++)
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mark_page_reserved(page);
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zero_page_mask = ((PAGE_SIZE << order) - 1) & PAGE_MASK;
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}
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static void *__kmap_pgprot(struct page *page, unsigned long addr, pgprot_t prot)
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{
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enum fixed_addresses idx;
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unsigned long vaddr, flags, entrylo;
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unsigned long old_ctx;
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pte_t pte;
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int tlbidx;
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BUG_ON(Page_dcache_dirty(page));
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preempt_disable();
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pagefault_disable();
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idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1);
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idx += in_interrupt() ? FIX_N_COLOURS : 0;
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vaddr = __fix_to_virt(FIX_CMAP_END - idx);
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pte = mk_pte(page, prot);
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#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
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entrylo = pte_to_entrylo(pte.pte_high);
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#else
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entrylo = pte_to_entrylo(pte_val(pte));
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#endif
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local_irq_save(flags);
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old_ctx = read_c0_entryhi();
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write_c0_entryhi(vaddr & (PAGE_MASK << 1));
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write_c0_entrylo0(entrylo);
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write_c0_entrylo1(entrylo);
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#ifdef CONFIG_XPA
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entrylo = (pte.pte_low & _PFNX_MASK);
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writex_c0_entrylo0(entrylo);
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writex_c0_entrylo1(entrylo);
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#endif
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tlbidx = read_c0_wired();
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write_c0_wired(tlbidx + 1);
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write_c0_index(tlbidx);
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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tlbw_use_hazard();
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write_c0_entryhi(old_ctx);
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local_irq_restore(flags);
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return (void*) vaddr;
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}
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void *kmap_coherent(struct page *page, unsigned long addr)
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{
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return __kmap_pgprot(page, addr, PAGE_KERNEL);
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}
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void *kmap_noncoherent(struct page *page, unsigned long addr)
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{
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return __kmap_pgprot(page, addr, PAGE_KERNEL_NC);
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}
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void kunmap_coherent(void)
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{
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unsigned int wired;
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unsigned long flags, old_ctx;
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local_irq_save(flags);
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old_ctx = read_c0_entryhi();
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wired = read_c0_wired() - 1;
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write_c0_wired(wired);
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write_c0_index(wired);
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write_c0_entryhi(UNIQUE_ENTRYHI(wired));
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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tlbw_use_hazard();
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write_c0_entryhi(old_ctx);
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local_irq_restore(flags);
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pagefault_enable();
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preempt_enable();
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}
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void copy_user_highpage(struct page *to, struct page *from,
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unsigned long vaddr, struct vm_area_struct *vma)
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{
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void *vfrom, *vto;
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vto = kmap_atomic(to);
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if (cpu_has_dc_aliases &&
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page_mapcount(from) && !Page_dcache_dirty(from)) {
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vfrom = kmap_coherent(from, vaddr);
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copy_page(vto, vfrom);
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kunmap_coherent();
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} else {
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vfrom = kmap_atomic(from);
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copy_page(vto, vfrom);
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kunmap_atomic(vfrom);
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}
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if ((!cpu_has_ic_fills_f_dc) ||
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pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
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flush_data_cache_page((unsigned long)vto);
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kunmap_atomic(vto);
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/* Make sure this page is cleared on other CPU's too before using it */
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smp_wmb();
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}
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void copy_to_user_page(struct vm_area_struct *vma,
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struct page *page, unsigned long vaddr, void *dst, const void *src,
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unsigned long len)
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{
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if (cpu_has_dc_aliases &&
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page_mapcount(page) && !Page_dcache_dirty(page)) {
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void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
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memcpy(vto, src, len);
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kunmap_coherent();
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} else {
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memcpy(dst, src, len);
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if (cpu_has_dc_aliases)
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SetPageDcacheDirty(page);
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}
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if (vma->vm_flags & VM_EXEC)
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flush_cache_page(vma, vaddr, page_to_pfn(page));
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}
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void copy_from_user_page(struct vm_area_struct *vma,
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struct page *page, unsigned long vaddr, void *dst, const void *src,
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unsigned long len)
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{
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if (cpu_has_dc_aliases &&
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page_mapcount(page) && !Page_dcache_dirty(page)) {
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void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
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memcpy(dst, vfrom, len);
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kunmap_coherent();
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} else {
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memcpy(dst, src, len);
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if (cpu_has_dc_aliases)
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SetPageDcacheDirty(page);
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}
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}
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EXPORT_SYMBOL_GPL(copy_from_user_page);
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void __init fixrange_init(unsigned long start, unsigned long end,
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pgd_t *pgd_base)
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{
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#ifdef CONFIG_HIGHMEM
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pgd_t *pgd;
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pud_t *pud;
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pmd_t *pmd;
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pte_t *pte;
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int i, j, k;
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unsigned long vaddr;
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vaddr = start;
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i = __pgd_offset(vaddr);
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j = __pud_offset(vaddr);
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k = __pmd_offset(vaddr);
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pgd = pgd_base + i;
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for ( ; (i < PTRS_PER_PGD) && (vaddr < end); pgd++, i++) {
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pud = (pud_t *)pgd;
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for ( ; (j < PTRS_PER_PUD) && (vaddr < end); pud++, j++) {
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pmd = (pmd_t *)pud;
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for (; (k < PTRS_PER_PMD) && (vaddr < end); pmd++, k++) {
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if (pmd_none(*pmd)) {
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pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
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set_pmd(pmd, __pmd((unsigned long)pte));
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BUG_ON(pte != pte_offset_kernel(pmd, 0));
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}
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vaddr += PMD_SIZE;
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}
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k = 0;
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}
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j = 0;
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}
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#endif
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}
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unsigned __weak platform_maar_init(unsigned num_pairs)
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{
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struct maar_config cfg[BOOT_MEM_MAP_MAX];
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unsigned i, num_configured, num_cfg = 0;
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phys_addr_t skip;
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for (i = 0; i < boot_mem_map.nr_map; i++) {
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switch (boot_mem_map.map[i].type) {
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case BOOT_MEM_RAM:
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case BOOT_MEM_INIT_RAM:
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break;
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default:
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continue;
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}
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skip = 0x10000 - (boot_mem_map.map[i].addr & 0xffff);
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cfg[num_cfg].lower = boot_mem_map.map[i].addr;
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cfg[num_cfg].lower += skip;
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cfg[num_cfg].upper = cfg[num_cfg].lower;
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cfg[num_cfg].upper += boot_mem_map.map[i].size - 1;
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cfg[num_cfg].upper -= skip;
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cfg[num_cfg].attrs = MIPS_MAAR_S;
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num_cfg++;
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}
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num_configured = maar_config(cfg, num_cfg, num_pairs);
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if (num_configured < num_cfg)
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pr_warn("Not enough MAAR pairs (%u) for all bootmem regions (%u)\n",
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num_pairs, num_cfg);
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return num_configured;
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}
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void maar_init(void)
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{
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unsigned num_maars, used, i;
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phys_addr_t lower, upper, attr;
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static struct {
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struct maar_config cfgs[3];
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unsigned used;
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} recorded = { { { 0 } }, 0 };
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if (!cpu_has_maar)
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return;
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/* Detect the number of MAARs */
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write_c0_maari(~0);
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back_to_back_c0_hazard();
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num_maars = read_c0_maari() + 1;
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/* MAARs should be in pairs */
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WARN_ON(num_maars % 2);
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/* Set MAARs using values we recorded already */
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if (recorded.used) {
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used = maar_config(recorded.cfgs, recorded.used, num_maars / 2);
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BUG_ON(used != recorded.used);
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} else {
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/* Configure the required MAARs */
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used = platform_maar_init(num_maars / 2);
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}
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/* Disable any further MAARs */
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for (i = (used * 2); i < num_maars; i++) {
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write_c0_maari(i);
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back_to_back_c0_hazard();
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write_c0_maar(0);
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back_to_back_c0_hazard();
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}
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if (recorded.used)
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return;
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pr_info("MAAR configuration:\n");
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for (i = 0; i < num_maars; i += 2) {
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write_c0_maari(i);
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back_to_back_c0_hazard();
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upper = read_c0_maar();
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write_c0_maari(i + 1);
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back_to_back_c0_hazard();
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lower = read_c0_maar();
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attr = lower & upper;
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lower = (lower & MIPS_MAAR_ADDR) << 4;
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upper = ((upper & MIPS_MAAR_ADDR) << 4) | 0xffff;
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pr_info(" [%d]: ", i / 2);
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if (!(attr & MIPS_MAAR_V)) {
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pr_cont("disabled\n");
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continue;
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}
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pr_cont("%pa-%pa", &lower, &upper);
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if (attr & MIPS_MAAR_S)
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pr_cont(" speculate");
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pr_cont("\n");
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/* Record the setup for use on secondary CPUs */
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if (used <= ARRAY_SIZE(recorded.cfgs)) {
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recorded.cfgs[recorded.used].lower = lower;
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recorded.cfgs[recorded.used].upper = upper;
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recorded.cfgs[recorded.used].attrs = attr;
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recorded.used++;
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}
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}
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}
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#ifndef CONFIG_NEED_MULTIPLE_NODES
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int page_is_ram(unsigned long pagenr)
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{
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int i;
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for (i = 0; i < boot_mem_map.nr_map; i++) {
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unsigned long addr, end;
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switch (boot_mem_map.map[i].type) {
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case BOOT_MEM_RAM:
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case BOOT_MEM_INIT_RAM:
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break;
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default:
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/* not usable memory */
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continue;
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}
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addr = PFN_UP(boot_mem_map.map[i].addr);
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end = PFN_DOWN(boot_mem_map.map[i].addr +
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boot_mem_map.map[i].size);
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if (pagenr >= addr && pagenr < end)
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return 1;
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}
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return 0;
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}
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void __init paging_init(void)
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{
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unsigned long max_zone_pfns[MAX_NR_ZONES];
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unsigned long lastpfn __maybe_unused;
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pagetable_init();
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#ifdef CONFIG_HIGHMEM
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kmap_init();
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#endif
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#ifdef CONFIG_ZONE_DMA
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max_zone_pfns[ZONE_DMA] = MAX_DMA_PFN;
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#endif
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#ifdef CONFIG_ZONE_DMA32
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max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
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#endif
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max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
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lastpfn = max_low_pfn;
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#ifdef CONFIG_HIGHMEM
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max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
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lastpfn = highend_pfn;
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if (cpu_has_dc_aliases && max_low_pfn != highend_pfn) {
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printk(KERN_WARNING "This processor doesn't support highmem."
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" %ldk highmem ignored\n",
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(highend_pfn - max_low_pfn) << (PAGE_SHIFT - 10));
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max_zone_pfns[ZONE_HIGHMEM] = max_low_pfn;
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lastpfn = max_low_pfn;
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}
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#endif
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free_area_init_nodes(max_zone_pfns);
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}
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#ifdef CONFIG_64BIT
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static struct kcore_list kcore_kseg0;
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#endif
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static inline void mem_init_free_highmem(void)
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{
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#ifdef CONFIG_HIGHMEM
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unsigned long tmp;
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for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
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struct page *page = pfn_to_page(tmp);
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if (!page_is_ram(tmp))
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SetPageReserved(page);
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else
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free_highmem_page(page);
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}
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#endif
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}
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void __init mem_init(void)
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{
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#ifdef CONFIG_HIGHMEM
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#ifdef CONFIG_DISCONTIGMEM
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#error "CONFIG_HIGHMEM and CONFIG_DISCONTIGMEM dont work together yet"
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#endif
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max_mapnr = highend_pfn ? highend_pfn : max_low_pfn;
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#else
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max_mapnr = max_low_pfn;
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#endif
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high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
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maar_init();
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free_all_bootmem();
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setup_zero_pages(); /* Setup zeroed pages. */
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mem_init_free_highmem();
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mem_init_print_info(NULL);
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#ifdef CONFIG_64BIT
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if ((unsigned long) &_text > (unsigned long) CKSEG0)
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/* The -4 is a hack so that user tools don't have to handle
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the overflow. */
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kclist_add(&kcore_kseg0, (void *) CKSEG0,
|
|
0x80000000 - 4, KCORE_TEXT);
|
|
#endif
|
|
}
|
|
#endif /* !CONFIG_NEED_MULTIPLE_NODES */
|
|
|
|
void free_init_pages(const char *what, unsigned long begin, unsigned long end)
|
|
{
|
|
unsigned long pfn;
|
|
|
|
for (pfn = PFN_UP(begin); pfn < PFN_DOWN(end); pfn++) {
|
|
struct page *page = pfn_to_page(pfn);
|
|
void *addr = phys_to_virt(PFN_PHYS(pfn));
|
|
|
|
memset(addr, POISON_FREE_INITMEM, PAGE_SIZE);
|
|
free_reserved_page(page);
|
|
}
|
|
printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
|
|
}
|
|
|
|
#ifdef CONFIG_BLK_DEV_INITRD
|
|
void free_initrd_mem(unsigned long start, unsigned long end)
|
|
{
|
|
free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
|
|
"initrd");
|
|
}
|
|
#endif
|
|
|
|
void (*free_init_pages_eva)(void *begin, void *end) = NULL;
|
|
|
|
void __init_refok free_initmem(void)
|
|
{
|
|
prom_free_prom_memory();
|
|
/*
|
|
* Let the platform define a specific function to free the
|
|
* init section since EVA may have used any possible mapping
|
|
* between virtual and physical addresses.
|
|
*/
|
|
if (free_init_pages_eva)
|
|
free_init_pages_eva((void *)&__init_begin, (void *)&__init_end);
|
|
else
|
|
free_initmem_default(POISON_FREE_INITMEM);
|
|
}
|
|
|
|
#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
|
|
unsigned long pgd_current[NR_CPUS];
|
|
#endif
|
|
|
|
/*
|
|
* gcc 3.3 and older have trouble determining that PTRS_PER_PGD and PGD_ORDER
|
|
* are constants. So we use the variants from asm-offset.h until that gcc
|
|
* will officially be retired.
|
|
*
|
|
* Align swapper_pg_dir in to 64K, allows its address to be loaded
|
|
* with a single LUI instruction in the TLB handlers. If we used
|
|
* __aligned(64K), its size would get rounded up to the alignment
|
|
* size, and waste space. So we place it in its own section and align
|
|
* it in the linker script.
|
|
*/
|
|
pgd_t swapper_pg_dir[_PTRS_PER_PGD] __section(.bss..swapper_pg_dir);
|
|
#ifndef __PAGETABLE_PMD_FOLDED
|
|
pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned_bss;
|
|
#endif
|
|
pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned_bss;
|